MT9044AP1 Zarlink Semiconductor, Inc., MT9044AP1 Datasheet - Page 17

• Manufacturer Part Number: MT9044AP1
• Description: Framer: Framer Circuit: T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9044
Data Sheet
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a
mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has
settled to a steady state.
In the case of the MT9044, the output signal phase continuity is maintained to within ±5ns at the instance (over one
frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type of
mode change, may accumulate up to ±200ns over many frames. The rate of change of the ±200ns phase shift is
limited to a maximum phase slope of approximately 5ns/125us. This meets the maximum phase slope requirement
of Bellcore GR-1244-CORE (81ns/1.326ms).
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) synchronizer loop filter
iv) synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9044 loop filter and
limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently,
phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical
Characteristics - Performance for maximum phase lock time.
MT9044 and Network Specifications
The MT9044 fully meets all applicable PLL requirements (intrinsic jitter/wander, jitter/wander tolerance,
jitter/wander transfer, frequency accuracy, frequency holdover accuracy, capture range, phase change slope and
MTIE during reference rearrangement) for the following specifications.
1. Bellcore GR-1244-CORE June 1995 for Stratum 3, Stratum 4 Enhanced and Stratum 4
2. AT&T TR62411 (DS1) December 1990 for Stratum 3, Stratum 4 Enhanced and Stratum 4
3. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4
4. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. ITU-T I.431 March 1993
9. ITU-T G.813 August 1996 for Option1 clocks for 2048 kbit/s interfaces
10. ITU-T G.812 June 1998 for type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces
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Zarlink Semiconductor Inc.