MT9044AL1 Zarlink Semiconductor, Inc., MT9044AL1 Datasheet - Page 10

• Manufacturer Part Number: MT9044AL1
• Description: Dual Reference Frequency Selectable Digital PLL with Multiple Clock Outputs for T1/E1 (ITU-T G.812 type IV), Stratum (3, 4, 4E) and STS-3/OC3 Systems
• Manufacturer: Zarlink Semiconductor, Inc.

MT9044
master clock may have a temperature coefficient of
±0.1ppm per degree C. So a 10 degree change in
temperature, while the MT9044 is in Holdover Mode
may result in an additional offset (over the
±0.05ppm) in frequency accuracy of ±1ppm, which is
much greater than the ±0.05ppm of the MT9044.
The other factor affecting accuracy is large jitter on
the reference input prior (30ms to 60ms) to the mode
switch. For instance, jitter of 7.5UI at 700Hz may
reduce the Holdover Mode accuracy from 0.05ppm
to 0.10ppm.
Freerun Mode
Freerun Mode is typically used when a master clock
source is required, or immediately following system
power-up
before
network
synchronization
is
achieved.
In Freerun Mode, the MT9044 provides timing and
synchronization signals which are based on the
master clock frequency (OSCi) only, and are not
synchronized to the reference signals (PRI and
SEC).
The accuracy of the output clock is equal to the
accuracy of the master clock (OSCi). So if a ±32ppm
output clock is required, the master clock must also
be ±32ppm. See Applications - Crystal and Clock
Oscillator sections.
10