MT9044AL1 Zarlink Semiconductor, Inc., MT9044AL1 Datasheet

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MT9044AL1

Manufacturer Part Number
MT9044AL1
Description
Dual Reference Frequency Selectable Digital PLL with Multiple Clock Outputs for T1/E1 (ITU-T G.812 type IV), Stratum (3, 4, 4E) and STS-3/OC3 Systems
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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Part Number:
MT9044AL1
Manufacturer:
ZARLINK
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Features
Applications
Supports AT&T TR62411 and Bellcore
GR-1244-CORE Stratum 3, Stratum 4 Enhanced
and Stratum 4 timing for DS1 interfaces
Supports ITU-T G.813 Option 1 clocks for 2048
kbit/s interfaces
Supports ITU-T G.812 Type IV clocks for 1,544
kbit/s interfaces and 2,048 kbit/s interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12
and TBR 13 timing for E1 interfaces
Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
Provides C1.5, C2, C3, C4, C6, C8, C16, and
C19 (STS-3/OC3 clock divided by 8) output
clock signals
Provides 5 different 8KHz framing pulses
Holdover frequency accuracy of 0.05 PPM
Holdover indication
Attenuates wander from 1.9Hz
Provides Time Interval Error (TIE) correction
Accepts reference inputs from two independent
sources
JTAG Boundary Scan
Synchronization and timing control for multitrunk
T1,E1 and STS-3/OC3 systems
ST-BUS clock and frame pulse sources
RSEL
LOS1
LOS2
TRST
TMS
TDO
SEC
TCK
PRI
TDI
OSCi
Master Clock
Reference
MS1
1149.1a
Select
MUX
IEEE
Reference
Select
Control State Machine
OSCo
Automatic/Manual
MS2
Selected
Reference
Corrector
Enable
RST
TIE
Figure 1 - Functional Block Diagram
Corrector
TCLR
HOLDOVER
Circuit
TIE
State
Select
Reference
Virtual
GTo
DS5058
Description
The MT9044 T1/E1/OC3 System Synchronizer
contains a digital phase-locked loop (DPLL), which
provides timing and synchronization signals for
multitrunk T1 and E1 primary rate transmission links
and STS-3/0C3 links.
The MT9044 generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.
The MT9044 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE Stratum 3, Stratum 4
Enhanced, and Stratum 4; and ETSI ETS 300 011;
and ITU-T G.813 Option 1 for 2048 kbit/s interfaces.
It will meet the jitter/wander tolerance, jitter/wander
transfer, intrinsic jitter/wander, frequency accuracy,
capture range, phase change slope, holdover
frequency
specifications.
Guard Time
Impairment
Monitor
Circuit
DPLL
Input
T1/E1/OC3 System Synchronizer
State
Select
GTi
MT9044AP
MT9044AL
VDD
and
Feedback
VSS
Ordering Information
MTIE
FS1
-40 to +85 ° C
Frequency
Interface
Select
Output
Circuit
MUX
ISSUE 5
requirements
FS2
44 Pin PLCC
44 Pin MQFP
APLL
MT9044
for
January 2001
C19o
C1.5o
C3o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
ACKi
ACKo
these
1

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MT9044AL1 Summary of contents

Page 1

Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces • Supports ITU-T G.812 Type IV clocks for 1,544 ...

Page 2

MT9044 VDD 7 OSCo 8 OSCi 9 VSS 10 F16o 11 MT9044AP 12 RSP 13 F0o TSP 14 F8o 15 C1. AVDD ...

Page 3

Pin Description (continued) Pin # Pin # Name PLCC MQFP 12 6 RSP Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse, which marks the end of an ST-BUS frame. This is typically used for ...

Page 4

MT9044 Pin Description (continued) Pin # Pin # Name PLCC MQFP 34 28 LOS1 Primary Reference Loss (TTL Input). Typically, external equipment applies a logic high to this input when the PRI reference signal is lost or invalid. The logic ...

Page 5

Functional Description The MT9044 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 shows the functional block diagram which is described in the ...

Page 6

MT9044 from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback signal) ...

Page 7

In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30ms to 60ms) ...

Page 8

MT9044 Input Impairment Monitor This circuit monitors the input signal to the DPLL and automatically enables the (Auto-Holdover) when the frequency of the incoming signal is outside the auto-holdover capture range (See AC Electrical Characteristics - Performance). This includes a ...

Page 9

MS2 MS1 Control 0 0 MANUAL 0 1 MANUAL 1 0 MANUAL 1 1 AUTO State Machine Control Table 3 - Operating Modes and States Manual Control Manual Control should be used when either very simple MT9044 control is required, ...

Page 10

MT9044 master clock may have a temperature coefficient of ±0.1ppm per degree degree change in temperature, while the MT9044 is in Holdover Mode may result in an additional offset (over the ±0.05ppm) in frequency accuracy of ...

Page 11

Description Input Controls MS2 MS1 RSEL GTi Legend Change / Not Valid MTIE State ...

Page 12

MT9044 Description Input Controls LOS2 LOS1 GTi RST Legend Change MTIE State ...

Page 13

MT9044 Measures of Performance The following are some synchronizer performance indicators and their corresponding definitions. Intrinsic Jitter Intrinsic jitter is the jitter produced synchronizing circuit and is measured at its output measured by applying a reference signal with ...

Page 14

MT9044 the storage value is determined while the device is in Normal Mode and locked to an external reference signal. The absolute Master Clock (OSCi) accuracy of the MT9044 does not affect Holdover accuracy, but the change in OSCi accuracy ...

Page 15

MT9044 and Network Specifications The MT9044 fully meets all requirements (intrinsic jitter/wander, jitter/wander tolerance, jitter/wander transfer, frequency accuracy, frequency holdover accuracy, capture range, phase change slope and MTIE rearrangement) for the following specifications. 1. Bellcore GR-1244-CORE June 1995 for Stratum ...

Page 16

MT9044 CTS CXO-65-HG-5-C-20.0MHz Frequency: 20MHz Tolerance: 25ppm 0C to 70C Rise & Fall Time: 8ns (0.5V 4.5V 50pF) Duty Cycle: 45% to 55% The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9044, ...

Page 17

An unsymmetrical Guard Time Circuit is shown in Figure 12. MT9044 GTo R C 150kΩ 1kΩ GTi R P 1kΩ Figure 12 - Unsymmetrical Guard Time Circuit Figure 13 shows a typical timing example of an ...

Page 18

MT9044 Reset Circuit A simple power up reset circuit with about a 50us reset low time is shown in Figure 14. Resistor R for protection only and limits current into the RST pin during power down conditions. The reset low ...

Page 19

To Line 1 MT9075 DSTo TTIP To DSTi TX Line TRING XFMR F0i RTIP C4i To RRING RX Line RxFP XFMR LOS To Line 2 MT9075 DSTo TTIP DSTi To TRING TX Line XFMR F0i RTIP C4i RRING To RX ...

Page 20

MT9044 To E1 Line MT9075 DSTo TTIP DSTi To TX Line TRING XFMR F0i RTIP C4i To RRING RX Line RxFP XFMR LOS MT90840 To OC3 Line STo0-7 PDo0-7 STi0-7 To PPFTo TX Line XFMR F0i PDi0-7 C4b To PCKR ...

Page 21

Absolute Maximum Ratings* - Parameter 1 Supply voltage 2 Voltage on any pin 3 Current on any pin 4 Storage temperature 5 PLCC package power dissipation 6 MQFP package power dissipation * Exceeding these values may cause permanent damage. Functional ...

Page 22

MT9044 AC Electrical Characteristics - Performance Characteristics 1 Freerun Mode accuracy with OSCi at Holdover Mode accuracy with OSCi at Capture range with OSCi at Phase lock time 11 Output phase ...

Page 23

AC Electrical Characteristics - Input/Output Timing Characteristics 1 Reference input pulse width high or low 2 Reference input rise or fall time 3 8kHz reference input to F8o delay 4 1.544MHz reference input to F8o delay 5 2.048MHz reference input ...

Page 24

MT9044 PRI/SEC 8kHz PRI/SEC 1.544MHz PRI/SEC 2.048MHz F8o NOTES: 1. Input to output delay values are valid after a TRST or RST with no further state changes Figure 20 - Input to Output Timing (Normal Mode) F8o F0o F16o t ...

Page 25

F8o C2o RSP TSP F8o MS1,2 LOS1,2 RSEL, GTi Figure 23 - Input Controls Setup and Hold Timing AC Electrical Characteristics - Intrinsic Jitter Unfiltered Characteristics 1 Intrinsic jitter at F8o (8kHz) 2 Intrinsic jitter at F0o (8kHz) 3 Intrinsic ...

Page 26

MT9044 AC Electrical Characteristics - C1.5o (1.544MHz) Intrinsic Jitter Filtered Characteristics 1 Intrinsic jitter (4Hz to 100kHz filter) 2 Intrinsic jitter (10Hz to 40kHz filter) 3 Intrinsic jitter (8kHz to 40kHz filter) 4 Intrinsic jitter (10Hz to 8kHz filter) † ...

Page 27

AC Electrical Characteristics - 2.048MHz Input to 2.048 MHz Output Jitter Transfer Characteristics 1 Jitter at output for 1Hz@3.00UIpp input 2 with 40Hz to 100kHz filter 3 Jitter at output for 3Hz@2.33UIpp input 4 with 40Hz to 100kHz filter 5 ...

Page 28

MT9044 AC Electrical Characteristics - 1.544MHz Input Jitter Tolerance Characteristics 1 Jitter tolerance for 1Hz input 2 Jitter tolerance for 5Hz input 3 Jitter tolerance for 20Hz input 4 Jitter tolerance for 300Hz input 5 Jitter tolerance for 400Hz input ...

Page 29

Notes: Voltages are with respect to ground (V ) unless otherwise stated. SS Supply voltage and operating temperature are as per Recommended Operating Conditions. Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels 1. ...

Page 30

Package Outlines Dim D General- (lead coplanarity) A Notes Not ...

Page 31

...

Page 32

Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45) A1 0.01 - (0.25) A2 0.077 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 BSC ...

Page 33

Package Outlines 160-Pin Dim Min 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 ...

Page 34

For more information about all Zarlink products visit our Web Site at www.zarlink.com ’ ’ “ ” ...

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