ATF16LV8C ATMEL Corporation, ATF16LV8C Datasheet - Page 5

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ATF16LV8C

Manufacturer Part Number
ATF16LV8C
Description
High- Performance EE PLD
Manufacturer
ATMEL Corporation
Datasheet

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Input Test Waveforms and
Measurement Levels:
t
Pin Capacitance
(f = 1 MHz, T = 25°C)
Note:
Power Up Reset
The ATF16LV8C’s registers are designed to reset during
power up. At a point delayed slightly from V
V
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
lowing conditions are required:
1. The V
2. The signals from which the clock is derived must
3. After T
R
C
C
RST
, t
IN
OUT
F
volts.
remain stable during T
be met before driving the clock term high.
, all registers will be reset to the low state. As a result,
< 1.5ns (10% to 90%)
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
CC
PR
rise must be monotonic from below 0.7
, all input and feedback setup times must
CC
(1)
actually rises in the system, the fol-
PR
.
Typ
5
6
CC
crossing
Max
8
8
Output Test Loads:
Commercial
Note:
Parameter
T
V
PR
RST
Similar devices are tested with slightly different loads.
These load differences may affect output signals’ delay
and slew rate. Atmel devices are tested with sufficient
margins to meet compatible devices.
R1 = 316
R2 = 348
Description
Power-Up
Reset Time
Power-Up
Reset
Voltage
Units
pF
pF
3.3V
Conditions
V
V
Typ
600
2.5
CL = 35 pF
OUTPUT
PIN
IN
OUT
= 0V
= 0V
1,000
Max
3.0
Units
ns
V
5

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