MT18VDDT6472 Micron, MT18VDDT6472 Datasheet - Page 17

• Manufacturer Part Number: MT18VDDT6472
• Description: 200-Pin DDR SDRAM SODIMMs (x72)
• Manufacturer: Micron

NOTES (continued)
21. The refresh period 64ms. This equates to an
22. The valid data window is derived by achieving
23. Referenced to each output group: x4 = DQS with
32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
average refresh rate of 15.625µs for 128MB module
or 7.8125µs for the 256MB module. However, an
AUTO REFRESH command must be asserted at
least once every 140.6µs for the 128MB module or
70.3µs for the 256MB module; burst refreshing or
posting by the DRAM controller greater than eight
refresh cycles is not allowed.
other specifications -
(
directly porportional with the clock duty cycle and
a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of
45/55. Functionality is uncertain when operating
beyond a 45/55 ratio. The data valid window
derating curves are provided below for duty cycles
ranging between 50/50 and 45/55.
DQ0–DQ3; x8 = DQS with DQ0–DQ7; x16 = LDQS
with DQ0–DQ7; and UDQS with DQ8–DQ15.
t
QH =
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
HP -
50/50
3.750
2.500
3.400
t
QHS). The data valid window derates
—— -75 @
—— -8 @
—— -75 @
—— -8 @
49.5/50.5
#
u
n
l
3.700
3.350
2.463
t
HP (
t
t
CK = 10ns
CK = 8ns
t
CK = 7.5ns
t
CK = 10ns
t
CK/2),
3.650
49/51
2.425
3.300
t
DQSQ, and
48.5/52.5
3.600
2.388
3.250
DERATING DATA VALID WINDOW
3.550
48/52
t
QH
2.350
3.200
Clock Duty Cycle
(
t
QH -
17
47.5/53.5
3.500
t
DQSQ)
2.313
3.150
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
26. CK and CK# input slew rate must be 1V/ns
27. DQ and DM input slew rates must not deviate from
result in a fail value. CKE is HIGH during RE-
FRESH command period (
LOW (i.e., during standby).
the input must:
a) Sustain a constant slew rate from the current AC
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to
( 2V/ns if measured differentially).
DQS by more than 10%. If the DQ/DM/DQS slew
rate is less than 0.5V/ns, timing must be derated:
50ps must be added to
100mv/ns reduction in slew rate. If slew rate
exceeds 4V/ns, functionality is uncertain.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3.450
47/53
level through to the target AC level, V
V
maintain at least the target DC level, V
V
184-pin DDR SDRAM DIMMs
2.275
3.100
IH
IH
(
(
AC
DC
256MB, 512MB (ECC x72)
).
).
46.5/54.5
3.400
2.238
3.050
3.350
46/54
2.200
3.000
t
DS and
t
RFC [MIN]) else CKE is
45.5/55.5
3.300
2.163
2.950
t
DH for each
©2002, Micron Technology, Inc.
3.250
45/55
2.900
2.125
IL
IL
(
AC
(
DC
) or
) or