MT18VDDT6472 Micron, MT18VDDT6472 Datasheet

MT18VDDT6472

Manufacturer Part Number

MT18VDDT6472

Description

200-Pin DDR SDRAM SODIMMs (x72)

Manufacturer

Micron

Datasheet

1.MT18VDDT6472.pdf (25 pages)

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DDR SDRAM

DIMM MODULE

FEATURES

• 184-pin dual in-line memory module (DIMM)

• Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM

• ECC-optimized pinout

• 256MB (32 Meg x 72), 512MB (64 Meg x 72)

• V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

• Internal, pipelined double data rate (DDR) architec-

• Bidirectional data strobe (DQS) transmitted/

• Differential clock inputs (CK and CK# - can be

• Four internal device banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.6µs (MT18VDDT3272AG), 7.8125µs

• Serial Presence Detect (SPD) with EEPROM

• Fast data transfer rates PC2100 or PC1600

• Programmable READ CAS latency

• Gold-plated edge contacts

PART NUMBERS AND TIMING PARAMETERS

NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for

32, 64 Meg x 72 DDR SDRAM DIMMs

DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02

PART NUMBER

MT18VDDT3272AG-26A__

MT18VDDT3272AG-265__

MT18VDDT3272AG-202__

MT18VDDT6472AG-26A__

MT18VDDT6472AG-265__

MT18VDDT6472AG-202__

components

aligned with data for WRITEs

ture; two data accesses per clock cycle

received with data—i.e., source-synchronous data

capture

multiple clocks, CK0/CK0#, CK1/CK1#, etc.)

(MT18VDDT6472AG) maximum average periodic

refresh interval

DDSPD

= V

current revision codes. Example: MT18VDDT6472AG-265A1

= +2.2V to +5.5V

Q= +2.5V ±0.2V

MARKING DENSITY

PART

-26A

-265

-202

-265

-202

MODULE CONFIGURATION

256MB

512MB

32 Meg x 72

64 Meg x 72

32 Meg x 72

64 Meg x 72

MT18VDDT3272AG - 256MB

MT18VDDT6472AG - 512MB

For the latest data sheet, please refer to the Micron Web

site:

ADDRESS TABLE

OPTIONS

• Package

• Frequency/CAS Latency

Refresh Count

Row Addressing

Device Bank Addressing

Device Configuration

Column Addressing

Module Bank Addressing

Unbuffered

184-pin DIMM (gold)

266 MHz/CL = 2 (133 MHz DDR SDRAMs)

266 MHz/CL = 2.5 (133 MHz DDR SDRAMs) -265

200 MHz/CL = 2 (100 MHz DDR SDRAMs)

www.micron.com/datasheets

TRANSFER

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2.1 GB/s

1.6 GB/s

2.1 GB/s

1.6 GB/s

184-pin DDR SDRAM DIMMs

RATE

256MB, 512MB (ECC x72)

DATA FREQUENCY

MEMORY CLOCK/

184-Pin DIMM

7.5ns/266 Mb/s

10ns/200 Mb/s

MO-206

4 (BA0, BA1)

4K (A0–A11)

16 Meg x 8

1K (A0–A9)

2 (S0#, S1#)

256MB

(CL -

LATENCY

MARKING

4 (BA0, BA1)

8K (A0–A12)

32 Meg x 8

2 (S0#, S1#)

1K (A0–A9)

2.5-3-3

RCD -

2-3-3

2-2-2

2-3-3

2-2-2

512MB

-26A

-202

RP)

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