MT16VDDF12864HG-40B Micron, MT16VDDF12864HG-40B Datasheet - Page 20

• Manufacturer Part Number: MT16VDDF12864HG-40B
• Description: DRAM Module, 128M x 64, 200-Pin DDR SDRAM SODIMM
• Manufacturer: Micron

09005aef80b577fa
DDAF16C64_128x64HG_A.fm - Rev. A 5/03 EN
37. This maximum value is derived from the refer-
38. For slew rates greater than 1V/ns the (LZ) transi-
39. During Initialization, V
40. The current Micron part operates below the slow-
41. For -40B, I
42. Random addressing changing and 50 percent of
160
140
120
100
80
60
40
20
0
Figure 8: Pull-Down Characteristics
0.0
enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for
(MAX) will prevail over
(MAX) condition.
t
tion will start about 310ps earlier.
be equal to or less than V
V
even if V
of 42 W of series resistance is used between the V
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
SDRAM device at 100 MHz.
data changing at every transfer.
DQSCK (MIN) +
TT
may be 1.35V maximum during power up,
0.5
DD
DD
/V
3
DD
N
t
HZ (MAX) and the last DVW.
is specified to be 35mA per DDR
Q are 0.0V, provided a minimum
t
RPRE (MAX) condition.
1.0
t
LZ (MIN) will prevail over
V
V
OUT
OUT
DD
(V)
(V)
t
DQSCK (MAX) +
DD
Q, V
1.5
+ 0.3V. Alternatively,
TT
, and V
2.0
Minimum
REF
t
RPST
must
t
HZ
TT
2.5
20
43. Random addressing changing and 100 percent of
44. CKE must be active (high) during the entire time a
45. IDD2N specifies the DQ, DQS, and DM to be
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
Figure 9: Pull-Up Characteristics
REF later.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MB, 1GB (x64) PC3200
0.5
200-PIN DDR SODIMM
1.0
V
DD
Q - V
OUT
(V)
1.5
©2003 Micron Technology, Inc.
2.0
2.5