LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 255
LM3S3768
Manufacturer Part Number
LM3S3768
Description
Lm3s3768 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S3768.pdf
(755 pages)
- Current page: 255 of 755
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10.1.6
10.2
Table 10-1. GPIO Pad Configuration Examples
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
June 02, 2008
Configuration
Digital Input (GPIO)
Digital Output (GPIO)
Open Drain Input
(GPIO)
Open Drain Output
(GPIO)
Open Drain
Input/Output (I
Digital Input (Timer
CCP)
Digital Input (QEI)
Digital Output (PWM)
Digital Output (Timer
PWM)
Digital Input/Output
(SSI)
Digital Input/Output
(UART)
Analog Input
(Comparator)
Digital Output
(Comparator)
2
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
Initialization and Configuration
The GPIO modules may be accessed via two different memory apertures. The legacy aperture is
backwards-compatible with previous Stellaris parts and offers two-cycle access time to all GPIO
registers. The high-speed aperture offers the same register map but provides single-cycle access
times. These apertures are mutually exclusive. The aperture enabled for a given GPIO port is
controlled by the appropriate bit in the GPIOHSCTL register (see page 91).
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the four JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 10-1 on page 255
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 10-2 on page 256 shows how a rising edge interrupt would be configured for
pin 2 of a GPIO port.
C)
GPIO Register Bit Value
AFSEL
0
0
0
0
1
1
1
1
1
1
1
0
1
DIR
X
X
X
X
X
X
X
X
0
1
0
1
0
ODR
a
0
0
1
1
1
0
0
0
0
0
0
0
0
DEN
Preliminary
1
1
1
1
1
1
1
1
1
1
1
0
1
PUR
?
?
X
X
X
?
?
?
?
?
?
0
?
PDR
?
?
X
X
X
?
?
?
?
?
?
0
?
DR2R
X
X
X
X
X
?
?
?
?
?
?
?
?
DR4R
LM3S3768 Microcontroller
X
X
X
X
X
?
?
?
?
?
?
?
?
DR8R
X
X
X
X
X
?
?
?
?
?
?
?
?
SLR
X
X
X
X
X
?
?
?
?
?
?
?
?
255
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