LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 172
LM3S3768
Manufacturer Part Number
LM3S3768
Description
Lm3s3768 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S3768.pdf
(755 pages)
- Current page: 172 of 755
- Download datasheet (7Mb)
Reset
Reset
Type
Type
Internal Memory
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
172
Bit/Field
31:2
RO
RO
1
0
31
15
0
0
RO
RO
Register 6: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
30
14
0
0
RO
RO
29
13
reserved
0
0
PMASK
AMASK
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0
9
0
0x0
reserved
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the controller. If set, a programming-generated interrupt is promoted
to the controller. Otherwise, interrupts are recorded but suppressed from
the controller.
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
controller. If set, an access-generated interrupt is promoted to the
controller. Otherwise, interrupts are recorded but suppressed from the
controller.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
PMASK
R/W
RO
17
0
1
0
June 02, 2008
AMASK
R/W
RO
16
0
0
0
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