LM3S8933 Luminary Micro, Inc, LM3S8933 Datasheet - Page 534
LM3S8933
Manufacturer Part Number
LM3S8933
Description
Lm3s8933 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S8933.pdf
(588 pages)
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Signal Tables
534
Table 20-6. Signals by Signal Name
Pin Number
M10
M12
M11
Pin Name
CAN0Rx
CAN0Tx
ERBIAS
CMOD0
CMOD1
ADC0
ADC1
ADC2
ADC3
CCP0
CCP1
CCP2
CCP3
C0+
C0-
C0o
C1+
C1-
C1o
C2+
C2-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Name
WAKE
OSC1
HIB
Pin Number
D12
E12
E11
B10
L10
K10
F10
J10
F11
M1
M1
M2
B1
A1
B3
B2
A7
A6
B7
G1
G2
E1
K3
C4
C5
H3
K5
K6
B6
F1
L2
L6
J3
Preliminary
Pin Type
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer Type
Buffer Type
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
Description
An external input that brings the processor out
of hibernate mode when asserted.
Main oscillator crystal output.
An output that indicates the processor is in
hibernate mode.
Description
Analog-to-digital converter input 0.
Analog-to-digital converter input 1.
Analog-to-digital converter input 2.
Analog-to-digital converter input 3.
Analog comparator 0 positive input
Analog comparator 0 negative input
Analog comparator 0 output
Analog comparator positive input
Analog comparator 1 negative input
Analog comparator 1 output
Analog comparator positive input
Analog comparator 2 negative input
CAN module 0 receive
CAN module 0 transmit
Capture/Compare/PWM 0
Capture/Compare/PWM 1
Capture/Compare/PWM 2
Capture/Compare/PWM 3
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
12.4 KOhm resistor (1% precision) used
internally for Ethernet PHY.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
July 25, 2008
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