LM3S8933 Luminary Micro, Inc, LM3S8933 Datasheet - Page 463

• Manufacturer Part Number: LM3S8933
• Description: Lm3s8933 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

17.2.4
17.3
July 25, 2008
and be used with a third 16-bit free-running timer to capture a more accurate timestamp for the
transmit or receive packet. This feature can be used with a protocol such as IEEE-1588 to provide
more accurate timestamps of the synchronization packets, improving the overall accuracy of the
protocol.
Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
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Initialization and Configuration
To use the Ethernet Controller, the peripheral must be enabled by setting the EPHY0 and EMAC0
bits in the RCGC2 register. The following steps can then be used to configure the Ethernet Controller
for basic operation.
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A frame has been received into an empty RX FIFO
A frame transmission error has occurred
A frame has been transmitted successfully
A frame has been received with no room in the RX FIFO (overrun)
A frame has been received with one or more error conditions (for example, FCS failed)
An MII management transaction between the MAC and PHY layers has completed
One or more of the following PHY layer conditions occurs:
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Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value would be 4.
Program the MACIA0 and MACIA1 register for address filtering.
Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
Program the MACRCTL register to reject frames with bad FCS using a value of 0x08.
Auto-Negotiate Complete
Remote Fault
Link Status Change
Link Partner Acknowledge
Parallel Detect Fault
Page Received
Receive Error
Jabber Event Detected
Preliminary
LM3S8933 Microcontroller
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