LM3S8933 Luminary Micro, Inc, LM3S8933 Datasheet - Page 10

• Manufacturer Part Number: LM3S8933
• Description: Lm3s8933 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10. Master Burst RECEIVE .................................................................................................. 389
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 390
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 391
Figure 15-13. Slave Command Sequence ............................................................................................ 392
Figure 16-1.
Figure 16-2.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 19-1.
Figure 19-2.
Figure 22-1.
Figure 22-2.
Figure 22-3.
Figure 22-4.
Figure 22-5.
Figure 22-6.
Figure 22-7.
Figure 22-8.
Figure 22-9.
Figure 22-10. JTAG TRST Timing ........................................................................................................ 556
Figure 22-11. External Reset Timing (RST) .......................................................................................... 557
Figure 22-12. Power-On Reset Timing ................................................................................................. 558
Figure 22-13. Brown-Out Reset Timing ................................................................................................ 558
Figure 22-14. Software Reset Timing ................................................................................................... 558
Figure 22-15. Watchdog Reset Timing ................................................................................................. 558
Figure 23-1.
Figure 23-2.
10
START and STOP Conditions ......................................................................................... 382
Complete Data Transfer with a 7-Bit Address ................................................................... 383
R/S Bit in First Byte ........................................................................................................ 383
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 386
Master Single RECEIVE ................................................................................................. 387
Master Burst SEND ....................................................................................................... 388
CAN Module Block Diagram ........................................................................................... 417
CAN Bit Time ................................................................................................................ 424
Ethernet Controller Block Diagram .................................................................................. 458
Ethernet Controller ......................................................................................................... 458
Ethernet Frame ............................................................................................................. 460
Analog Comparator Module Block Diagram ..................................................................... 503
Structure of Comparator Unit .......................................................................................... 504
Comparator Internal Reference Structure ........................................................................ 505
100-Pin LQFP Package Pin Diagram .............................................................................. 515
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 516
Load Conditions ............................................................................................................ 547
I
External XTLP Oscillator Characteristics ......................................................................... 552
Hibernation Module Timing ............................................................................................. 553
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 554
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 554
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 555
JTAG Test Clock Input Timing ......................................................................................... 556
JTAG Test Access Port (TAP) Timing .............................................................................. 556
100-Pin LQFP Package .................................................................................................. 559
108-Ball BGA Package .................................................................................................. 561
2
C Timing ..................................................................................................................... 550
Preliminary
2
C Bus ............................................................... 383
July 25, 2008