LM3S6952 Luminary Micro, Inc, LM3S6952 Datasheet - Page 17

• Manufacturer Part Number: LM3S6952
• Description: Lm3s6952 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Synchronous Serial Interface (SSI) ............................................................................................ 345
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Inter-Integrated Circuit (I
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Ethernet Controller ...................................................................................................................... 417
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July 25, 2008
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 357
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 359
SSI Data (SSIDR), offset 0x008 ...................................................................................... 361
SSI Status (SSISR), offset 0x00C ................................................................................... 362
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 364
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 365
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 367
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 368
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 369
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 370
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 371
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 372
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 373
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 374
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 375
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 376
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 377
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 378
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 379
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 380
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 381
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 426
Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 428
Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 429
Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 430
Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 431
Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 432
Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 434
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 396
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 397
C Master Data (I2CMDR), offset 0x008 ......................................................................... 401
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 402
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 403
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 404
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 405
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 406
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 407
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 409
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 410
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 412
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 413
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 414
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 415
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 416
2
C) Interface ........................................................................................ 382
Preliminary
LM3S6952 Microcontroller
17