LM3S6422 Luminary Micro, Inc, LM3S6422 Datasheet - Page 412
LM3S6422
Manufacturer Part Number
LM3S6422
Description
Lm3s6422 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S6422.pdf
(473 pages)
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Signal Tables
412
Pin Number
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
XTALNPHY
Pin Name
SSI0Clk
SSI0Fss
SSI0Rx
SSI0Tx
VCCPHY
ERBIAS
GNDPHY
VDD25
CCP3
U0Rx
U0Tx
CCP1
RXIN
RXIP
VDD
GND
PC6
PC5
C1+
C1o
PC4
PA0
PA1
PA2
PA3
PA4
PA5
VDD
GND
PA6
GND
NC
NC
NC
NC
Preliminary
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
I
Buffer Type
Analog
Analog
Analog
Analog
Power
Power
Power
Power
Power
Power
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
-
-
-
Description
XTALN of the Ethernet PHY
No connect. Leave the pin electrically
unconnected/isolated.
No connect. Leave the pin electrically
unconnected/isolated.
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
No connect. Leave the pin electrically
unconnected/isolated.
GPIO port C bit 6
Capture/Compare/PWM 3
GPIO port C bit 5
Analog comparator positive input
Analog comparator 1 output
GPIO port C bit 4
GPIO port A bit 0
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
GPIO port A bit 1
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
GPIO port A bit 2
SSI module 0 clock
GPIO port A bit 3
SSI module 0 frame
GPIO port A bit 4
SSI module 0 receive
GPIO port A bit 5
SSI module 0 transmit
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
GPIO port A bit 6
Capture/Compare/PWM 1
No connect. Leave the pin electrically
unconnected/isolated.
VCC of the Ethernet PHY
RXIN of the Ethernet PHY
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Ground reference for logic and I/O pins.
RXIP of the Ethernet PHY
12.4 KOhm resistor (1% precision) used
internally for Ethernet PHY.
GND of the Ethernet PHY
July 25, 2008
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