LM3S1637 Luminary Micro, Inc, LM3S1637 Datasheet - Page 10

• Manufacturer Part Number: LM3S1637
• Description: Lm3s1637 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10. Master Burst RECEIVE .................................................................................................. 386
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 387
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 388
Figure 15-13. Slave Command Sequence ............................................................................................ 389
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 17-5.
Figure 17-6.
Figure 18-1.
Figure 18-2.
Figure 19-1.
Figure 19-2.
Figure 22-1.
Figure 22-2.
Figure 22-3.
Figure 22-4.
Figure 22-5.
Figure 22-6.
Figure 22-7.
Figure 22-8.
Figure 22-9.
Figure 22-10. External Reset Timing (RST) .......................................................................................... 517
Figure 22-11. Power-On Reset Timing ................................................................................................. 518
Figure 22-12. Brown-Out Reset Timing ................................................................................................ 518
Figure 22-13. Software Reset Timing ................................................................................................... 518
Figure 22-14. Watchdog Reset Timing ................................................................................................. 518
Figure 23-1.
Figure 23-2.
10
START and STOP Conditions ......................................................................................... 379
Complete Data Transfer with a 7-Bit Address ................................................................... 380
R/S Bit in First Byte ........................................................................................................ 380
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 383
Master Single RECEIVE ................................................................................................. 384
Master Burst SEND ....................................................................................................... 385
Analog Comparator Module Block Diagram ..................................................................... 413
Structure of Comparator Unit .......................................................................................... 414
Comparator Internal Reference Structure ........................................................................ 415
PWM Unit Diagram ........................................................................................................ 424
PWM Module Block Diagram .......................................................................................... 425
PWM Count-Down Mode ................................................................................................ 426
PWM Count-Up/Down Mode .......................................................................................... 426
PWM Generation Example In Count-Up/Down Mode ....................................................... 427
PWM Dead-Band Generator ........................................................................................... 427
QEI Block Diagram ........................................................................................................ 460
Quadrature Encoder and Velocity Predivider Operation .................................................... 462
100-Pin LQFP Package Pin Diagram .............................................................................. 477
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 478
Load Conditions ............................................................................................................ 510
I
Hibernation Module Timing ............................................................................................. 513
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 514
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 514
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 515
JTAG Test Clock Input Timing ......................................................................................... 516
JTAG Test Access Port (TAP) Timing .............................................................................. 516
JTAG TRST Timing ........................................................................................................ 516
100-Pin LQFP Package .................................................................................................. 519
108-Ball BGA Package .................................................................................................. 521
2
C Timing ..................................................................................................................... 513
Preliminary
2
C Bus ............................................................... 380
July 25, 2008