AD8191 Analog Devices, AD8191 Datasheet - Page 16

• Manufacturer Part Number: AD8191
• Description: 4:1 DVI/HDMI Switch with Equalization Preliminary Data Sheet (Rev. PrJ, 8/2006)
• Manufacturer: Analog Devices

AD8191
THEORY OF OPERATION
INTRODUCTION
The primary function of the AD8191 is to switch one of four
(HDMI or DVI) single-link sources to one output. Each
HDMI/DVI link consists of four differential, high speed
channels and four auxiliary single-ended, low speed control
signals. The high speed channels include a data-word clock and
three transition minimized differential signaling (TMDS) data
channels running at 10× the data-word clock frequency for data
rates up to 1.65 Gbps. The four low speed control signals are 5
V tolerant bidirectional lines that can carry configuration
signals, HDCP encryption, and other information; depending
upon the specific application.
All four high speed TMDS channels in a given link are identical;
that is, the pixel clock can be run on any of the four TMDS
channels.
Transmit and receive channel compensation is provided for the
high speed channels where the user can (manually) select
among a number of fixed settings.
The AD8191 switching logic has three modes: quad (one 4:1
DVI/HDMI link switch), dual (two 8:1 TMDS channel switch)
and single (one 16:1 TMDS channel switch).
The AD8191 has dual parallel and I
8 user-programmable I
programming values override any prior parallel programming
values.
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
VTTI power supply through a pair of single-ended 50 Ω on-
chip resistors, as shown in Figure 10. The input terminations
can be optionally disconnected for approximately 100 ms
following a source switch. The user can program which of the
16 high speed input channels employs this feature by selectively
setting the associated RX_PT bits in the input termination pulse
register. Additionally, all the input terminations can be
disconnected by programming the RX_TO bit in the receiver
settings register.
Figure 10. High-speed Input Simplified Schematic
2
P
C slave addresses. In all cases serial
P
2
P
C serial programming with
P
Rev. PrJ | Page 16 of 29
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually program the equalization level of the eight high
speed input channels by selectively setting the associated RX_EQ
bits in the receive equalizer register. No specific cable length is
suggested for a particular equalization setting because cable
performance varies widely between manufacturers; however, in
general, the equalization of the AD8191 can be set to 12 dB
without degrading the signal integrity, even for short input
cables. At the 12 dB setting, the AD8191 can equalize over 20
meters of 24 AWG cable at 1.65 Gbps.
OUTPUT CHANNELS
Each high-speed output differential pair is terminated to the
+3.3V VTTO power supply through a 50Ω on-chip resistor
(Figure 11). This termination is user-selectable; it can be turned
on or off by programming the TX_PTO bit of the Transmitter
Settings Register.
The output termination resistors of the AD8191 back-terminate
the output TMDS transmission lines. These back-terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8191
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
The AD8191 output has a disable feature that places the outputs
in a tri-state mode. This mode is enabled by setting the HS_EN
bit of the high speed device modes register. Larger wire-OR’ e d
arrays can be constructed using the AD8191 in this mode.
The AD8191 requires output termination resistors when the
high speed outputs are enabled. Termination can be internal
and/or external. The internal terminations of the AD8191 are
enabled by setting the TX_PTO bit of the transmitter settings
register (the default upon reset). External terminations can be
provided either by on-board resistors or by the input
termination resistors of an HDMI/DVI receiver. If both
internal and external terminations are provided, set the output
current level to 20 mA by programming the TX_OCL bit of the
transmitter settings register (the default upon reset). If only
Figure 11. High-speed Output Simplified Schematic
Preliminary Technical Data