AD8191 Analog Devices, AD8191 Datasheet - Page 11

• Manufacturer Part Number: AD8191
• Description: 4:1 DVI/HDMI Switch with Equalization Preliminary Data Sheet (Rev. PrJ, 8/2006)
• Manufacturer: Analog Devices

Preliminary Technical Data
Table 15. Single Auxiliary Switch Mode Mapping
RECEIVER SETTINGS REGISTER
RX_TO:
on/off select bit
Table 16. RX_TO Description
INPUT TERMINATION PULSE REGISTERS 1 AND 2
RX_PT[X]:
source switch select bit
Table 17. RX_PT[X] Description
AUX_CH[3:0]
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
RX_TO
0b
1b
RX_PT[X]
0b
1b
U
High-speed (TMDS) channels input termination
U
Description
Input termination off
Input termination on (can be pulsed on and off
according to settings in the Input Termination Pulse
Register)
High-speed (TMDS) input channel “X” pulse-on-
Description
Input termination for TMDS channel “X” always
connected when source is switched
Input termination for TMDS channel “X”
disconnected for 100msec when source switched
AUX_COM[3:0]
AUX_A0
AUX_A1
AUX_A2
AUX_A3
AUX_B0
AUX_B1
AUX_B2
AUX_B3
AUX_C0
AUX_C1
AUX_C2
AUX_C3
AUX_D0
AUX_D1
AUX_D2
AUX_D3
Description
Auxiliary channel A0
switched to output
Auxiliary channel A1
switched to output
Auxiliary channel A2
switched to output
Auxiliary channel A3
switched to output
Auxiliary channel B0
switched to output
Auxiliary channel B1
switched to output
Auxiliary channels B2
switched to output
Auxiliary channels B3
switched to output
Auxiliary channels C0
switched to output
Auxiliary channels C1
switched to output
Auxiliary channels C2
switched to output
Auxiliary channels C3
switched to output
Auxiliary channels D0
switched to output
Auxiliary channels D1
switched to output
Auxiliary channels D2
switched to output
Auxiliary channels D3
switched to output
Rev. PrJ | Page 11 of 29
Table 18. RX_PT[X] Mapping
RECEIVE EQUALIZER REGISTERS 1 AND 2
RX_EQ[X]:
select bit
Table 19. RX_EQ[X] Description
Table 20. RX_EQ[X] Mapping
RX_PT[X]
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RX_EQ[X]
0b
1b
RX_EQ[X]
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
U
High-speed (TMDS) input “X” equalization level
Corresponding Input TMDS Channel
B0
B1
B2
B3
A0
A1
A2
A3
C3
C2
C1
C0
D3
D2
D1
D0
Corresponding Input TMDS Channel
Description
Low equalization (6dB)
High equalization (12dB)
B0
B1
B2
B3
A0
A1
A2
A3
C3
C2
C1
C0
D3
D2
D1
AD8191