TN28F010-150 Intel Corporation, TN28F010-150 Datasheet - Page 16

• Manufacturer Part Number: TN28F010-150
• Description: 28F010 1024K (128K X 8) CMOS FLASH MEMORY
• Manufacturer: Intel Corporation

28F010
3.0
3.1
Flash memories are often used in larger memory
arrays. Intel provides two read control inputs to
accommodate multiple memory connections. Two-
line control provides for:
a. the lowest possible memory power dissipation
b. complete assurance that output bus contention
To efficiently use these two control inputs, an
address decoder output should drive chip-enable,
while the system’s read signal controls all flash
memories and other parallel memories. This
assures that only enabled memory devices have
active outputs, while deselected devices maintain
the low power standby condition.
3.2
Flash
require
designers are interested in three supply current
(I
peaks produced by falling and rising edges of chip-
enable. The capacitive and inductive loads on the
device outputs determine the magnitudes of these
peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 µF ceramic
capacitor connected between V
between V
Place the high-frequency, low-inherent inductance
capacitors as close as possible to the devices.
Also, for every eight devices, a 4.7 µF electrolytic
capacitor should be placed at the array's power
supply connection, between V
capacitor will overcome voltage slumps caused by
printed circuit board trace inductance, and will
supply charge to the smaller capacitors as needed.
16
CC
) issues—standby, active, and transient current
and,
will not occur.
DESIGN CONSIDERATIONS
memory
Two-Line Output Control
Power Supply Decoupling
careful
PP
and V
power-switching
SS
device
.
decoupling.
CC
and V
CC
characteristics
and V
SS
. The bulk
SS
System
, and
3.3
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V
supply trace. The V
current for programming. Use similar trace widths
and layout considerations given the V
Adequate V
decrease V
3.4
The 28F010 is designed to offer protection against
accidental erasure or programming during power
transitions.
indifferent as to which power supply, V
powers up first. Power supply sequencing is not
required. Internal circuitry in the 28F010 ensures
that the command register is reset to the read mode
on power-up.
A system designer must guard against active writes
for V
Since both WE# and CE# must be low for a
command write, driving either to V
writes. The control register architecture provides an
added level of protection since alteration of memory
contents only occurs after successful completion of
the two-step command sequences.
3.5
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain
code or data when the system is off. Table 4
illustrates the power dissipated when updating the
28F010.
CC
voltages above V
V
Boards
Power-Up/Down Protection
28F010 Power Dissipation
PP
PP
PP
Upon
voltage spikes and overshoots.
Trace on Printed Circuit
supply traces and decoupling will
PP
power-up,
pin supplies the memory cell
LKO
when V
the
CC
IH
PP
28F010
power bus.
PP
will inhibit
PP
is active.
or V
power
CC
is
,