MCP6271R Microchip Technology Inc., MCP6271R Datasheet - Page 3

• Manufacturer Part Number: MCP6271R
• Description: 170 ?a, 2 Mhz Rail-to-rail Op Amp
• Manufacturer: Microchip Technology Inc.

Looking Forward To Technology Migration
By Bonnie C. Baker, Microchip Technology Inc.
The industry is laying the groundwork as we speak. The
geometries of digital and analog integrated circuit silicon
processes are shrinking. As a consequent, IC devices continue
to have lower power-supply voltage requirements, silicon areas
and prices. I personally have witnessed geometry migration from
1.2 microns all the way down to 0.25 microns. I am finding that a
device function manufactured with a 0.7 micron process may not
work as well if I change to a 0.25 micron process.
What is that all about?! I theoretically haven’t changed anything,
but it appears that my circuits present an argument to the
contrary. Of course, I have the option of not selecting devices
that have migrated to smaller geometries, which is a very bad
idea for a forward-thinking engineer. By not participating in this
industry trend, I turn down the added benefits of lower power-
supply voltages, faster speeds and lower cost. Not very smart!
My only line of defense is to design with the expectation that
geometries are going to continue to get smaller. I know that
smaller geometry devices are able to support lower power-supply
voltages. This helps me with my power consumption issues, but
ESD (electrostatic discharge) is less than optimum. Not only
are smaller geometry devices less able to absorb high-voltage
transients, but they lack robustness around high currents. The
manufacture’s standards are as high as ever with a 2000 Vrms
to 4000 Vrms ESD tolerance (Human Body Model). However,
their tests look for catastrophic failures while the end user can
experience RAM contamination because of EMI (electromagnetic
interference) and EFT (electrical fast transients) signals.
However, there are several areas that I can focus on, such as
protection circuits (MOVs, transient suppressors), microcontroller
or processor pin protection (I/O, interrupt, reset pins), or firmware
recovery techniques (WDT, register refresh), etc. All of these
techniques help produce a robust design, but I get the biggest
bang-for-the-buck when I optimize my layout.
If you want to join this smaller-geometry migration wave, look for
places in your layout where spikes and glitches can enter your,
soon to be, sensitive circuits. A great place is to look at the
power-supply traces. In a typical circuit, buck or boost converters
generate the power-supply signals. On top of this type of noisy
supply, your can receive EFT on top of the power voltages. This
EFT will manifest itself as voltage or current spikes. Remember,
with higher order geometry designs the circuit works just fine
in your current layout. A general rule of thumb going forward is
to minimize these effects by managing your power and ground
traces (or planes). Finally, your circuit has always required
decouple or bypass capacitors, but now the proper selection is
critical.
Techniques To Minimize Noise
Figure 1 illustrates a few examples of what to do and not do.
Figure 1: Connecting several devices with one ground and V
trace, (a) can became a candidate for ground and power-supply
loops. This topology also enhances power-supply glitches. Having
ground or V
Creating a ground and V
solution (c) between the three. However, the best solution is to
have separate ground and power-supply planes (d) in a multi-layer
board.
You have probably heard all of these suggestions before and a
multitude of other useful hints beyond this short column. If so,
that is a good sign. Since you’re a descent engineer, you probably
have discovered what you need and don’t need in your circuit. I
congratulate you. But, change is in the wind. As you move into
new silicon geometries, you need to implement those seemingly
ancient layout rules. Optimize your layout with power glitches
in mind. Add protection circuits such as MOVs and transient
suppressors. Protect the I/O, interrupt and reset pins of your
controller or processor. Use firmware recovery techniques such
as WDT or register refresh so they contain the correct values. All
of these techniques will foster the production of a robust design.
(Single Layer)
a) Poor
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Analog and Interface Guide – Volume 2
jumper (b) is a better solution but not great.
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(Single Layer)
trace from device to device is a better
b) Good
(Multi-Layer)
(Single Layer)
d) Best
c) Better
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