SSD1859 Solomon Systech, SSD1859 Datasheet - Page 18

• Manufacturer Part Number: SSD1859
• Description: 128 x 80 STN LCD Segment / Common 4 G/S Drive
• Manufacturer: Solomon Systech

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HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter, which translates the low voltage output signal to the required
driving voltage. The output is shifted out with an internal FRM clock, which comes from the Display
Timing Generator. The voltage levels are given by the level selector, which is synchronized with the
internal M signal.
Reset Circuit
When
input is low, the chip is initialized to the following:
RES
1. Page address is set to 0
2. Column address is set to 0
3. Display is OFF
4. Display Start Line is set to 0 (GDDRAM page 0, D0)
5. Display Offset is set to 0 (COM0 is mapped to ROW0)
6. 128x80 display mode
7. Normal/Reverse Display is Normal
8. N-line Inversion Register is 0
9. Entire Display is OFF
10. Power Control Register (VC, VR, VF) is set to (0,0,0)
11. 3X Booster is selected
12. Internal Resistor Ratio register is set to 0H
13. Software Contrast is set to 32
14. LCD Bias Ratio is set to 1/10
15. Normal scan direction of COM outputs
16. Segment remap is disabled (SEG0 display column address 0)
17. Internal oscillator is OFF
18. Test mode is OFF
19. Temperature coefficient is set to PTC0 (-0.05%)
20. Icon display line is OFF
When RESET command is issued, the following parameters are initialized only:
1. Page address is set to 0
2. Column address is set to 0
3. Initial Display Line is set to 0 (point to display RAM page 0, D0)
4. Internal Resistor Ratio register is set to 0H
5. Software Contrast is set to 32
Solomon Systech
Dec 2003
P 18/48 Rev 1.0
SSD1859