I2C-Interface Philips Semiconductors / NXP Semiconductors, I2C-Interface Datasheet - Page 3

• Manufacturer Part Number: I2C-Interface
• Description: Programming the 12C Interface
• Manufacturer: Philips Semiconductors / NXP Semiconductors

Figure 2:
or driven low by another device on th
Getting on the Bus
Three
the macro framework.
procedure.
er devices
under
the SDA line without waiting for a trar
sition.
to pull the serial data off the bus whe
of the clock and data lines. As with th
one for each transition
SDA lines.
named to reflect the physical operation
they perform.
SCL_Low
a low state.
other hand, relinquishes
SCL line, which may then be pulIed hig
bus. A read-modify-write
used for the bit manipulation
other 6 bits of Port 2 are not affecte
by the 12C operations.
ly the master transmit (Listing One, pag
polling of the SCL line that gives rise
an importanc
bit-by-bit baud-rate
vice on the IzC bus may hoid the clot
line low m order
more rime (a serial wait state). The otl
to poll the SCL line uric11 the slow d<
vice releases control of the clock.
function is simply to return the state c
the clock is valid.
polling macros. there are four types-
Philips Semiconductors
The
The .‘domg” macros control the stat
12C Specific information
procedures
the category
%Get_SDA_Bit LS
%Get_SDA_&t
always drives the SCL line
Flowcba??jx- PC transmrt
on the bus are then force
%Relea.se_SCL_Higb,
The .‘domg
feature of 12C: automatit
For example,
I
were created
to stall the bus fc
adjustment.
of “watching.”
stop
macro also fal
I’ll describe
used pnmanl
of the XL c
control of th
’
operation
macros
so mat th
I
%Drzve
Any df
on th
usm
or
ar
11
I
t
I
mit procedure,
far pointer to the message
sion, the byte count for the message,
and the slave address.
far procedure
procedures.
conform
guage caUing convention,
a conversion
cedures save only the state of the mcxd-
shed segment
forms error checking
rameters
message. The maximum message length
is set at 64 Kbytes by the segmentation
of the 80186 memory
strictton could be removed
ing code to handle segment boundanes.
The transmit procedure
direction bit tn the slave address
sure that a reception
neously
back to the calling procedure
the AK regrster. (The exact code
Listing One.)
getting
bus to determme
in progress.
dure aborts with the appropriate
code. If the bus is free, a start condition
IS generated,
fined as a high-to-low
with SCL high followed
pause. These waveforms
erated with the
tween the stop and start condiuons,
cluding addresstng
as an &bit data value followed
acknowledge
ural nested loop structure
of the procedure:
ing Two, page 1081, as they represent
the needs of most 12C users. The slave
procedure
not be described
a.5 follows:
2. The master generates
3. The master broadcasts
4. The master transrmts 0 or more bytes
5. The master generates
oM~ec~_~or_Br&+-ee
% WaU_4_ 7-d
106~ and master receive functions (List-
I. The master polls the bus to see if it
The stack frame for the master trans-
The master transmit
The first step in sending a message is
All communication
An 12C master transmission
(ACK) from the addressed
each byte.
is in use.
tion on the bus.
dress and expects
of data, expecting
tion and releases the bus.
on the
indicated.
before attempting
to a specific
is long and intricate and will
No attempt
If so, the transmit
would be trivial. The pro-
The start condition
bit. This lead to the nat-
registers.
calls are used in all the
macros.
I~CXA.A~~, includes
%Dnve_SDA_Low
12C bus.
if any transactions
here.
see Figure 2.
and data, takes place
Errors are reported
on the Ik bus be-
an ACK following
on the passed pa-
an acknowledge
transition of SDA
Far pointers
simply polls the
space.
procedure
high-level
also checks the
was not erro-
are easily gen-
a stop condi-
a start condi-
was made to
although such
71
the slave ad-
by a 4.7_uS
for the body
for transrms-
The
to send the
by mciud-
slave.
proceeds
This re-
through
macro
proce-
by an
to en-
is de-
error
is in
lan-
per-
and
and
are
in-
a
Programming the 12C Interface
waveforms
sions. A bus collision occurs when two
bus simultaneously.
handles collisions with the simple rule:
line wins the bus.” To ensure
(the master transmit procedure)
bus, the SDA line is checked
er transmitting a 1. If a 0 is present, then
a collision
other master
and the transfer must be aborted.
loop after the 8 bits of data (or address)
have been transmitted.
from the addressed
is aborted
ceived. At the end of the ACK bit the
message length counter IS decremented.
Control is returned
more data remains, otherwrse a stop con-
dition is generated
rmt procedure
sult storage throughout
procedure.
ister is used to hold the current
(either
onto the SDA line. This elimmates
need for local data storage
procedure.
On the Receiving End
The
ceive transaction
those in transmission:
transmitung the 8 bits of each data byte.
propriate
masters attempt
“He who transmits the first 0 on the SDA
immediately checks for an acknowledge
1.
2. The master
Each transmitted
rial wait states and potential
Control
The
The inner
Registers are used for tntermediate
is
waiting
amount
steps involved
in use.
lh-ee distinct tasks
watching the bus,
implementing the
master
address
are involved in
driving the bus
L3 Dobbk Journal June 1992
data (SDA) and clock (SCL)
is turned
if an acknowledge
has occurred
whiIe checking
For example,
is pulling
loop
terminates.
generates
for
or data) bemg shifted
of
to gain control of the
are almost identical to
bit generates
and the master mu-is-
to the inner loop if
in an I’C master re-
IS responsible
the bus to see tf it
slave. The transfer
time, and
over to the outer
a specijiic
The 12C protocol
The outer loop
the body of the
the line low),
a start condi-
(because
the AH reg-
for both se-
within the
bus colli-
is not re-
whenev-
own the
that we
the ap-
value
an-
the
for
re-