I2C-Interface Philips Semiconductors / NXP Semiconductors, I2C-Interface Datasheet - Page 2

• Manufacturer Part Number: I2C-Interface
• Description: Programming the 12C Interface
• Manufacturer: Philips Semiconductors / NXP Semiconductors

Philips Semiconductors
tmct macros. The algorithms
you just need
your CPU watch, Walt. and do.
mon event during a transfer. The macn
delay by usmg the 8086 LOOP instruc
t1on with a couple of NOPs for tunmg
see Example l(a). Total execuuon
LS readily calculated from mstrucuon m
ing tables. The same macro IS ported t(
the 1960 architecture
Although
I? protocol (watching, welting, and dc
In9 can be compartmentalized
up the IlC driver are written with thesg
macros
need co understand
I?
%Wazt_4_ i_u.S implements
l*C Specific information
AH the basic bu1ldmg blocks of thj
For example, a
No
protocol
as the fmmework.
I
I
I
1
+7
I.
am a neophyte
Assert
to port these
Drive SCl_ Low
Wad 2.35 pS
to know
51t on SDA
4,7_uS
Nth Data
the mtncac1es of thg
1n Example
delay IS a corn
how to makf
,
I
I
,
routines-
lust such
You don
that makl
when
into dk
l(b:
t1mf
I
A few word5 about the target hardware
are 1n order before
Any 1mplementatlon
Serial Clock (SCLJ and Serial Data
cessor, which has two open-dram
on-chip.
P2.7 (SDA), are part of a larger &bit
port. Processon
ports can easdy implement
addition
Iacch.
and P2LTCH. are used to read and wnce
the state of the port pms. The 8OCl86EB
allows the spec1aMunct:on
be located
ry or I/O space.
non, I chose
I/O space, even though this iimted
choice
chitecture
modify-wnte
(an AND to I/O, for example):
only load and store (IN and OUT?. So
why did I iirmt myself? Agam, I had to
assume
nator for our customers
1ng my code.
Building the Fmmewark
Early on 1n development.
parution
physical
Example
comes to i960 programng,
problems
Hardware Dependencies
requires
lector),
lines. The code 1n this article was de-
s1gned for the 8OCl86EB embedded
implementation
Two spec1aMuncuon
%*DEFINE(Wait_4_i’_uS)
0-4
defme(Waltz_4_7_uS,’
Ob:
of instructions.
bidirectional
the lowest
processes
two open-drain
The two pms, ~2.6 ECL) and
my code macros according
of an eZxtemal open-collector
portmg the core macros.
1: cu) 8OCl8G tmplementatzon
does not provide
anywhere
IIWV
loop
nOP
noP
lda
cmpdeco
bne.t
instructIons
to leave the registers
wIthout opendram
of 4 7-1~5 wazt macro
For this 1mplementa-
mvolved
I
common
cx,
of the I?C protocol
$
0x17,
0, r4
Ob
discuss the code.
port pins for the
m either memo-
registers, P2PIN
The 80186 ar-
5
when
70
(or open-col-
i
1n I/O space
I
r4
I’C wKh the
registers
decided
in the 12C
for read-
I
denoml-
design-
hJd no
C
1t can
SDA)
ports
pr@
I/O
my
to
to
to
1n
# instruction
# so assume
# compare
I if
# brancn)
# ?he cmpdeco
# clocks
#
# 0x17
# at
;
;
;
;
; total =
; 15 * 62.5ns
Programming the i*C Interface
4
4*15+5
3
3 clocks
clocks
clocks
The LOOP instructIon
wait for a transItion on the appropnate
lm&ng
ample. the code necessarv to access the
stack frame IS not written as a macro,
whereas
clock line is. Thus was done to Isolate
Architecturedependent
from the more generic
lMacros were also not used for ‘.gray ar-
eas” such as the shtimg
which
and physical
tions that passed the litmus test fell m-
to the three aforementioned
of watchmg,
mm~mum time delay
mented
CX register, then branches
(in thus case 1t.self3 tf the result 1s non-
zero. The delay 1s (n-1)*15+5
where n 1s the starting value in the CX
register. All the delays were calculated
assuming
nanoseconds
works at lower CPU speeds because the
1% protocol
tlmmgs.
only ~‘accurate enough.”
mgs as close as I could get to the spec-
ified minimum
bit” polling loops. These pieces of code
12C line to occur before allowing execu-
t1on to contmue.
macros
lines; one for high-to-low transitions and
one for low-to-high
protocol.
port was not wntten as macros. For ex-
oj.4 7_US utazt macro: (b) 8096OCA
16MHz :h~s
!=O branch
The .walting” macros provide a fixed-
The “watching” macros are ‘spin-on-
(25 decxml)
= 65
In parallel
and decrement
75
IS both architecture
no clocks.
for each of the two I’C sIgna
usmg a simple LOOP $ delay.
clocks
Llr Dobbs Journals June 1992
the code needed
In fact, the delay macros
Code not d1rectiy mvoived m
clocks
= 4.69uS
nay be Issued
and bne.t
the acnons of a hardware
a ~~-MHZ clock
back
1s 4.69uS
waiting, and domg.
per clock). The code still
only specifies
m nature.
without
l
Cnmum.
There are two polling
(predict
3 = 75 clocks
(close
counter
Cogecher
transitions.
They are impie-
code sequences
decrements
undue tunmg.
in parallel
providing
1% funcuons.
The 1% func-
of serial data.
enough)
taken
to toggle the
to the target
dependent
in r4
categories
rate (62.5
mmimum
take
clocks,
3
The
tlm-
the
are
1%