EM6A9320 Etron Technology Inc., EM6A9320 Datasheet - Page 5

• Manufacturer Part Number: EM6A9320
• Description: 4M x 32 DDR SDRAM
• Manufacturer: Etron Technology Inc.

BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
Extended Mode Register Set
No-Operation
Device Deselect
Burst Stop
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Power Down Mode Entry Idle/Active
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Et ronT ech
Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any
applications using the single ended clocking, apply V
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK . Table 2 shows
the truth table for the operation commands.
Note: 1. V = Valid data, X = Don't Care, L = Low level, H = High level
Etron Confidential
V
V
V
V
NC
DDQ
SSQ
REF
SS
Command
2. CKE
3. These are states of bank designated by BA0, BA1signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
CKE
When this command is asserted in the burst cycle, device state is clock suspend mode.
n-1
n
Supply Ground: Ground
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply Reference Voltage for Inputs: +0.5 x V
signal is input level when commands are provided.
signal is input level one clock cycle before the commands are provided.
-
No Connect: These pins should be left unconnected.
(Power Down)
(Self Refresh)
Active
Active
Active
Active
Active
Active
Active
State
Idle
Any
Any
Idle
Idle
Any
Any
Idle
Idle
Idle
Any
(3)
(3)
(3)
(3)
(3)
(4)
(5)
Table 2. Truth Table (Note (1), (2) )
CKEn-1 CKEn DM BA1 BA0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
4Mx32 DDR SDRAM
X
X
X
X
X
X
X
X
X
X
X
H
H
H
X
X
X
L
L
REF
5
X
X
X
V
V
X
X
X
X
X
X
X
X
X
X
X
X
H
L
to CK# pin.
V
V
X
V
V
V
V
X
X
X
X
X
X
X
X
X
X
L
L
DDQ
H
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
L
A8 A11-A9, A7-0 CS# RAS# CAS# WE#
H
H
H
X
X
X
X
X
X
X
X
X
X
L
L
L
Row Address
OP code
Address
Column
A0~A7
X
X
X
X
X
X
X
X
X
X
X
X
Rev 0.3
EM6A9320
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
H
X
H
X
H
X
H
X
X
L
L
L
L
L
L
L
July. 2002
H
H
H
H
X
H
X
H
X
H
X
H
X
X
L
L
L
L
L
L
L
L
H
H
H
H
X
H
H
X
H
X
H
X
H
X
X
L
L
L
L
L
L
L