EM6607 EM Microelectronic, EM6607 Datasheet - Page 11

• Manufacturer Part Number: EM6607
• Description: Ultra-low power microcontroller
• Manufacturer: EM Microelectronic

4.6
RESET initialises the CPU as shown in the table below.
Table 7.
4.7
POR and Power-Check are supervising the V
guarantee proper operation after Power-On. The resetcold signal is released when the V
for the IC to function correctly.
During power-up of the EM6607 static POR (Power-On-Reset) cell supervising the V
give initial reset. Reset can be prolonged also with Power-Check function if enabled by metal option. In this case V
come above V
signal and starts to execute instructions.
When Power-Check is enabled a power-check logic is switched-on with POR signal high and starts to check periodically
V
check starts in the middle of quartz Cold-Start sequence – after first 16384 system clocks with the same timing as in normal
SVLD operation. If V
Quartz Cold-Start is finished and release System reset.
In case V
rising V
V
is high enough to avoid “grey” zone between static POR and V
IMPORTANT: special care should be taken, when Power Supply starts to fall close to or below V
of the SVLD
zone, which must be avoided for proper operation.
Copyright © 2005, EM Microelectronic-Marin SA
name
Program counter 0
Program counter 1
Program counter 2
stack pointer
index register
Carry flag
Zero flag
HALT
Instruction register
periphery registers
DD
DD
against the SVLD-V
becomes higher as V
CPU State after RESET
POR with Power-Check Reset
DD
DD
, it might happen that Quartz Cold-Start is finished. System reset will keep the EM6607 under reset until first time
Initial Value after RESET
< V
R
V
L1
L1
L1
of the SVLD described in Chapter
(1.3V) must be done. Between minimum V
, comparison will be repeated with every next 8 Hz system clock until V
DD
> V
L1
L1
level which keeps resetcold active high until V
L1
to guarantee good operating conditions (oscillator stabilized during its Cold-Start delay and V
bits
12
12
12
2
7
1
1
1
16
4
Power-Check condition is met and system reset will wait until first 32768 clocks needed for
symbol
PC0
PC1
PC2
SP
IX
CY
Z
HALT
IR
REG
(digital) which follows more or less the V
1 1
1 3 3 H
S upply Voltage Level Detector (SVLD) to release the circuit reset
1 3 4 H
initial value
$000 (as a result of Jump 0)
undefined
undefined
SP(0) selected
undefined
undefined
undefined
0
Jump 0
see peripheral memory map
DD
L1
supply of 1.2V and static POR level of 0.9V there is a grey
).
11
DD
> V
L1
. When used with external quartz first V
REG
with level of typ. 0.9V is checked to
DD
DD
DD
supply voltage is high enough
supply voltage on start-up to
> V
L1
DD
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. In case of a very slow
min. Frequent checking
EM6607
DD
must
DD
DD