AN2797 Freescale Semiconductor / Motorola, AN2797 Datasheet - Page 28

• Manufacturer Part Number: AN2797
• Description: Migrating from IBM 750GX to MPC7447A
• Manufacturer: Freescale Semiconductor / Motorola

Hardware Considerations
1. Use A[4-35] for 32 bit addressing, with A[0-3] pulled down if not in use.
2. In 32 bit mode AP[0] should be pulled up.
In the MPC7447A BMODE1 is sampled after HRESET is negated to the set the processor ID in MSSCR0[ID]. The
value of the processor ID is important in a multiprocessor system where one would want to define one processor
with the value 0 by negating BMODE1 and make that processor responsible for booting and configuring other
processors and system logic. Other processors would have BMODE1 tied high to differentiate. In this case the
processor 0 could also configure the other processors Processor ID Register, PIR, with unique values within the
system.
An another important point to make is the fact the MPC7447A supports up to 16 pipelined transactions configured
by MSSCR[DTQ]. Since it does not support out of order transactions, hence no DBWO, the Data Transaction Index,
DTI[0:3], should be pulled low.
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In 36 bit mode use AP[0:4] as follows:
AP[1] contains odd parity for A[4:11].
AP[2] contains odd parity for A[12:19].
AP[3] contains odd parity for A[20:27].
AP[4] contains odd parity for A[28:35].
AP[0] contains odd parity for A[0:3]
Signal Description
Data retry
Reservation
TLB invalidate synchronize
Migrating from IBM 750GX to MPC7447A, Rev. 1.0
Table 16. 60x Signal Differences
IBM 750GX
TLBISYNC
DRTRY
RSRV
MPC7447A
N/A
N/A
N/A
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