AN2536 Freescale Semiconductor / Motorola, AN2536 Datasheet - Page 21

• Manufacturer Part Number: AN2536
• Description: MC9328MX1 and MC9328MXL High Speed Layout Design Guidelines
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
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Use multi-layer PCBs that provide separate VCC and ground planes.
Add 10 to 30 ohm resistors in series to each of the switching outputs to limit the current flow into
each of the outputs.
Create synchronous designs that will not be affected by momentarily switching pins.
Assign I/O pins to minimize local bunching of output pins.
Place the power and ground pins next to each other. The total inductance will be reduced by mutual
inductance, since current flows in opposite directions in power and ground pins.
Use a bigger via size to connect the capacitor pad to the power and ground plane to minimize the
inductance in decoupling capacitors.
Use surface mount capacitors to minimize the lead inductance.
Use low effective series resistance (ESR) capacitors. The ESR should be < 400 ohm.
Each GND pin/via should be connected to the ground plane individually.
To add extra capacitance on the board, It is recommended to place a ground plane next to each power
(VCC) plane. This placement gives zero lead inductance and no ESR. The dielectric thickness
between the two planes should be ~5 mils.
Place suitable termination resistor to ensure impedance matching between the line impedance
(R
Recommendations for critical high speed routing, like SDRAMC related signals for 3.0V memory
bus
— Trace length under 4.5cm, less than 65 ohm, to maintain the metal delay within 940ps.
— Inductance value of that trace less than 40nH.
— Keep the trace capacitance within 20pF.
— Overall capacitive loading (including both trace and component) for all signals, Address, Data,
Recommendations for critical high speed routing, like SDRAMC related signals for 1.8V memory
bus
— Trace length under 4cm, less than 55 ohm, to maintain the metal delay within 800ps.
— Inductance value of that trace less than 28 nH.
— Keep the trace capacitance within 15 pF.
— From the data captured from the PDA form factor design, the following total capacitive loading
O
)and the terminating resistor (R
Control, and SDCLK, should be no greater than 30pF.
(including both trace and component) is recommended for the following signals:
– Address, Data, and Control signals: The Address bus displayed the highest total capacitive
– SDLCK signal: Due to the importance of this signal for latching information, and the fact
loading of 29.5pF, and this same maximum can be applied to similar signals such as the Data
and Control signals (like RAS, CAS, etc.). Thus we recommend a total capacitive loading
of less than 30pF for these signals.
that all the other signals are dependent upon the integrity of this signal, we highly
recommend a total capacitive loading of this signal to be less than 18pF.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC9328MX1/MXL Application Note
Go to: www.freescale.com
T
) is equal to the line impedance.
Design Guidelines on PCB
21