AN2536 Freescale Semiconductor / Motorola, AN2536 Datasheet - Page 14

• Manufacturer Part Number: AN2536
• Description: MC9328MX1 and MC9328MXL High Speed Layout Design Guidelines
• Manufacturer: Freescale Semiconductor / Motorola

MC9328MX1/MXL Case Study
Following is the requirement list we applied to this development board:
With the ADS ver1.1 PCB, we have measured the worst case trace from the SDCLK relative to Address,
Data or Controls signals. Also, the board vendor was able to perform a simulation of the ADS v1.1
memory signals routing and provide the trace data for these signals. From their simulation data and
concurrently from capturing the waveforms from this signal it was found that Address signal A2 is the
worst signal on the board relative to the SDCLK, providing the worst case set up time measurement. This
simulation data, as well as the captured waveforms can be found in Figure 22. Also, Figure 23 provides a
logical illustration of memory signals routing.
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Place the 32 kHz and 16 Mhz crystals close to the core and use short traces to connect the crystal to
the XTAL and EXTAL pins.
Prevent routing any high speed trace across or close to the 32 kHz crystal, 16 MHz crystal, XTAL
pins and EXTAL pins. If possible, it is recommended to place a “route keepout” area around the
crystal circuit.
The total metal delay of each high speed trace should be smaller than 940ps. This figure is based on
the worst case 32-bit system with two 4Mx16-bit SyncFlash devices (MT28S4M16LC-10) and two
16Mx16-bit SDRAMs (MT48LC16M16A2-75). This figure can be larger if fewer memory devices
are in the system or if SyncFlashs are not used. The setup time requirement of SyncFlash
(MT28S4M16LC-10) is at least 3ns while the setup time requirement of SDRAM
(MT48LC16M16A2-75) is at least 1.5ns. A longer trace will increase the rise time and the fall time
of the signals therefore the setup time of signals generated by the MC9328MX1/MXL will decrease
with increased trace length.
Place the memory devices with the larger setup time closer to the MC9328MX1/MXL and connect
them with shorter traces. For example, SyncFlash has a 3ns setup time and SDRAM has a 2ns setup
time. Therefore the SyncFlash should be placed closer to the MC9328MX1/MXL.
Connect the signal which has higher priority with shorter trace. The priority of the signals are as
follows:
Use as few vias as possible to avoid adding extra capacitance loading to the trace.
Use a Tee topology for the PCB layout of the trace to balance the delay between the MC9328MX1/
MXL to different memory devices. Figure 21 provides an illustration of this.
It is recommended to add one 0.01uF decoupling capacitor and one 0.1uF decoupling capacitor for
each memory device’s power supply to ground.
Signals
Priority
Highest
SDCLK Addr CAS RAS SDWE CS3 CS2 Data DQM SDCKE1 SDCKD0
Figure 21. Recommend Layout of Memory Devices
Freescale Semiconductor, Inc.
For More Information On This Product,
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MC9328MX1/MXL Application Note
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Go to: www.freescale.com
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