AN2505 Freescale Semiconductor / Motorola, AN2505 Datasheet - Page 9

• Manufacturer Part Number: AN2505
• Description: MSC8102 Asynchronous DSI Throughput
• Manufacturer: Freescale Semiconductor / Motorola

4.4 Broadcast Single Write Throughput
The maximum DSI single broadcast write performance is based on consecutive writes to MSC8102 M2 memory.
Figure 7 shows one broadcast write transaction obtained from the logic analyzer. The figure shows the host clock,
address lines, chip select, and write enable signal. The throughput for consecutive broadcast write accesses is
calculated to be 55.93 MB/s, which translates into approximately nine MSC8101 bus clock cycles. This value is
averaged over four consecutive broadcast write transactions. As for the DSI read and writes, the MSC8101 core
stalls for the duration of the transaction. If the SC140 core operates three times faster than the 60x-compatible bus
clock, the SC140 core stalls for 9× 3 = 27 core clock cycles. The broadcast write is clearly faster than the single
write transaction because the transfer acknowledge is not necessary since the host cannot determine which DSP
drove the
4.5 Host DMA Read Throughput
The maximum host DMA read performance is based on timings illustrated in Figure 8. The figure shows the host
clock, which is the MSC8101 system bus clock by which the UPM controls the external memory accesses. The
figure also illustrates the address lines, chip select, read enable signal, and transfer acknowledge signal. The
throughput for consecutive read accesses is calculated to be 61.28 MB/s, which translates into approximately 8.21
MSC8101 bus clock cycles averaged over four consecutive host DMA read transactions. DMA reduces the latency
when reading from consecutive memory locations, thus increasing the throughput beyond that obtained in a single
read transaction.
Freescale Semiconductor
Note: The DSI broadcast write mode is used to broadcast data to the multiple MSC8102s. In this type of
HTA
signal.
System Bus Clock
configuration, the
broadcast mode because there would be contention between these devices.
System Bus Clock
HTA/UPMWAIT
HWBS0/PWE0
HWBS0/PWE0
HCS/CS4
HBCS/CS3
Address
Address
Figure 7. Asynchronous Broadcast Single Write
MSC8102 Asynchronous DSI Throughput, Rev. 1
HTA
Figure 6. Asynchronous Single Write
signal is shared between the MSC8102s. The
HTA
is not needed for
Actual Throughput
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