AN2505 Freescale Semiconductor / Motorola, AN2505 Datasheet - Page 3

• Manufacturer Part Number: AN2505
• Description: MSC8102 Asynchronous DSI Throughput
• Manufacturer: Freescale Semiconductor / Motorola

2.2 MSC8102 DSI Timings
The DSI timings are different, depending on whether the host processor reads from the DSI, writes to the DSI, or
broadcasts data to multiple DSIs on multiple DSPs. The DSI communicates via a dual-strobe or a single-strobe
method. The timings for each method are similar. This application note references only dual-strobe mode since this
is the mode used to collect the throughput data for the DSI. This section illustrates the differences between reads,
writes, and broadcast writes for dual-strobe accesses.
2.2.1 DSI Read Timings
Figure 2 illustrates the timings for an asynchronous DSI read as indicated in the MSC8102 Technical Data sheet.
When the memory controller on the host processor is programmed, the MSC8102 DSI read timing specifications
must be met to complete the transaction properly. For a read transaction, the address of the memory location or
register must be driven first. Then, the host issues a chip select to enable the MSC8102 DSI. Since multiple
MSC8102 devices can be connected, the MSC8102 samples the
DSI is selected. If the
is accessed. The host continues the transaction by asserting the
Meanwhile, the data becomes available for the MSC8101. The typical handshaking procedure is complete when
the MSC8102 drives the
Freescale Semiconductor
HCID[0–4]
HA[11–29]
HWBSn
HD[0–63]
HDBSn
HRDS
HCID[0–3]
HTA
HTA
HDST
HCS
HRW
HTA
signal to notify the host processor that the data transfer is acknowledged.
signals match the CHIPID value that is located in DCIR internal register, the DSI
MSC8102 Asynchronous DSI Throughput, Rev. 1
Figure 2. DSI Asynchronous Read Timings
108
104
106
100
107
112
HRDS
HCID[0–3]
103
signal and then later deasserting the signal.
Asynchronous DSI Connections and Timings
signals to determine which MSC8102
105
101
102
111
109
110
3