AN2505 Freescale Semiconductor / Motorola, AN2505 Datasheet - Page 6

• Manufacturer Part Number: AN2505
• Description: MSC8102 Asynchronous DSI Throughput
• Manufacturer: Freescale Semiconductor / Motorola

Theoretical Throughput
3
When actual throughput measurements are obtained, it is good practice to have a theoretical value for comparison.
Most throughput measurements quoted by DSP manufacturers are based on timing values and timing diagrams
similar to those illustrated in Section 2, which do not necessarily represent what happens in the DSP. The
throughput measurements based on timings in a data sheet illustrate the performance the DSP can achieve, but host
processors typically cannot support this type of performance. For example, completing an asynchronous DSI read
transaction requires a minimum of 38.96 ns if the MSC8102 DSI operates at 70 MHz. This value comes from
adding the following timing values from Figure 2 and Figure 5:
The throughput is calculated by the following equation in terms of MB/second.
T = Throughput
N = Number of bytes transferred
t = Time of transaction
M = 2
If N = 8 bytes for one 64-bit transfer and t = 38.96 ns as calculated from the timings, the throughput is 195.83
MB/s. This is a large number for an asynchronous read transfer and is not representative of reality. Host processors
operating asynchronously generally do not meet this level of performance. What really happens during the read
transaction is that the MSC8102 device sends an
MSC8102ADS, the MSC8101 host must synchronize the
MSC8101 system bus clock cycles. The same synchronization must also occur for the deassertion of the
signal, which may increase the cycle count by one or two cycles.
6
111
112
201
202
No.
NOTES: 1.“Attributes” refers to the following signals:
20
Read/Write data strobe deassertion to output HTA high
impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
• DCR[HTADT] = 01
• DCR[HTADT] = 10
• DCR[HTADT] = 11
Read/Write data strobe assertion width
Host data input setup time before write data strobe
deassertion
Host data input hold time after write data strobe deassertion
Theoretical Throughput
•
•
•
= 1, 048, 576
Timing 100. Set-up time before strobe assertion (3.6 ns).
Timing 111. Read/Write data strobe deassertion to output
01 (5 ns + 14.28 ns).
Timing 112. Read/Write data strobe assertion width (1.8 ns + 14.28 ns).
and
HWBSn
.
Characteristics
Table 1. DSI Asynchronous Mode Timing (Continued)
MSC8102 Asynchronous DSI Throughput, Rev. 1
T = (N) / (t × M)
HTA
signal to acknowledge the transaction. On the
HTA
HCS
signal with the SIU, which may add one or two
, HA[11–29], HCID[0–4], HDST, HRW,
1.8 + T
HTA
Min
1.3
high impedance where DCR[HTADT] =
—
2
REFCLK
5 + (1.5 × T
5 + (2.5 × T
5 + T
Freescale Semiconductor
Max
—
—
—
REFCLK
REFCLK
REFCLK
HRDS
Equation 1
HTA
)
)
,
Unit
ns
ns
ns
ns
ns
ns