AN2497 Freescale Semiconductor / Motorola, AN2497 Datasheet - Page 5

• Manufacturer Part Number: AN2497
• Description: HCS08 Background Debug Mode versus HC08 Monitor Mode
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
HCS08 Background Debug Mode versus HC08 Monitor Mode
Figure 1
header with 0.025" square posts on 0.1" centers.
implementation in a typical HCS08 target system.
The BKGD pin is used for bidirectional communication between an external
host, such as a PC or development tool, and the target MCU. To keep this to a
single pin, a custom serial protocol was devised. (This protocol is also used as
the HC12 and HCS12 Family background communication protocol.) The
protocol is more tolerant of speed variations than the asynchronous protocol
used for ordinary RS-232 terminals, like that used for the HC08 monitor mode
communication. The BDC communication clock has two options, the CPU bus
clock or a special BDM clock that is defined for each HCS08 derivative. This
option allows a host to choose a faster FLL-based bus speed after the FLL has
stabilized. For more details, refer to the HCS08 Family Reference Manual and
the data book for the specific MCU.
There are two main methods to communicate with the target MCU through the
BDC. In the hardware method, the RESET pin is released after the BKGD and
RESET pins are pulled low, and then the BKGD pin is released. In this method,
the MCU enters the active background mode instead of the normal user mode.
The software method does not require a reset of the MCU. By sending
non-intrusive commands to the MCU, the user can communicate with the MCU
without disturbing the running application program. Background entry methods
will be discussed later.
Brief details of BDC commands are discussed in a later section.
Freescale Semiconductor, Inc.
For More Information On This Product,
HOST PC
shows the standard BDM connector. This is typically a 2 by 3 pin
Figure 2. Typical HCS08 System with BDM Access
Go to: www.freescale.com
PARALLEL
CABLE
NO CONNECT 3
NO CONNECT 5
Figure 1. BDM Connector
BKGD
BDM MULTILINK
INTERFACE POD
1
BDM
2
4
6
GND
RESET
V
DD
Figure 2
Background Debug Mode Interface
shows the BDM
6-PIN BDM CONNECTOR
TARGET SYSTEM
SEE FIGURE 1
AN2497/D
5