AN2400 Freescale Semiconductor / Motorola, AN2400 Datasheet - Page 5

• Manufacturer Part Number: AN2400
• Description: HCS12 NVM Guidelines
• Manufacturer: Freescale Semiconductor / Motorola

Flash Clock Divider
Register
MOTOROLA
state machine and charge-pump, thus allowing multiple Flash blocks and
EEPROM to be programmed or erased simultaneously.
The Flash and EEPROM are programmed in units of aligned words, i.e. two
bytes at a time. The data word is written to an even address, i.e. bit 0 of the
address is clear. This will result in the bytes at the even address and the even
address plus one being programmed.
The Flash memory is erased either in 512 byte sectors (1024 byte sectors for
the 128k byte block), or as a mass erase of an entire block. A sector is a distinct
division of Flash: 512 byte sectors start at addresses $x000, $x200, $x400,
$x600, $x800, $xA00, $xC00 and $xE00. 1024 bytes sectors start at addresses
$x000, $x400, $x800 and $xC00.
The EEPROM memory is erased either in 4 byte sectors, or as a mass erase
of the entire block. A sector is a distinct division of EEPROM: EEPROM sectors
start at addresses $xxx0, $xxx4, $xxx8 and $xxxC.
The command register, address register and data registers are buffered to
allow pipelined programming. Pipelined programming allows the next address,
data and command to be loaded while the current command is still executing,
thus reducing the overall programming time.
Flash (but not EEPROM) also has a mode called Burst programming. Burst
programming is invoked by pipelining program commands for words on the
same Flash row. A row is 64 bytes on 32k and 64k byte Flash blocks and 128
bytes on the 128k Flash block. Burst programming reduces the programming
time by keeping the high voltage generation switched on between program
commands on the same row. Burst programming is approximately twice as fast
as single word programming.
Flash and EEPROM are programmed and erased in very similar ways, and so
the following description applies equally to both. The two main registers used
during programming and erase operations are the Flash or EEPROM Status
register and the Flash or EEPROM Command register. The Flash or EEPROM
Clock Divider Register must be correctly initialised before programming or
erasure can begin.
The Flash Clock Divider register is shared between all Flash Blocks.
The EEPROM Clock Divider Register has identical bit definitions (bit names
start with E instead of F).
FDIVLD
Freescale Semiconductor, Inc.
7
For More Information On This Product,
PRDIV8
Figure 6. Flash Clock Divider Register (FCLKDIV)
Go to: www.freescale.com
6
HCS12 NVM Guidelines
FDIV5
5
FDIV4
4
FDIV3
3
FDIV2
2
Split-Gate Flash Memory
FDIV1
1
FDIV0
AN2400/D
0
5