AN2400 Freescale Semiconductor / Motorola, AN2400 Datasheet
AN2400
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AN2400 Summary of contents
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... Freescale Semiconductor, Inc. Application Note AN2400/D Rev. 3, 07/2003 HCS12 NVM Guidelines by Stuart Robb Applications Engineering Motorola, East Kilbride Introduction The HCS12 is the next generation of the industry standard 68HC12 16-bit microcontrollers. The HCS12 is built around a high performance CPU with bus frequencies 25MHz, and is complemented by on-chip peripherals such as timers, analogue-to-digital converters and advanced serial communications modules such as CAN, SPI, SCI and IIC ...
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... Freescale Semiconductor, Inc. AN2400/D The reader should refer to the relevant Flash (or EEPROM) Block User Guide for complete details of all Flash/EEPROM registers. The reader should also refer to the relevant microcontroller User Guide for current Flash/EEPROM electrical specifications, particularly data retention, write-erase cycles and erase/programming timings ...
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... For More Information On This Product, Wordline Source Figure 2. One quarter of a Split-Gate Flash Word Figure VDD 0V VDD >>VDD Figure 3. Programming a ‘0101’ pattern into Split-Gate Flash HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Split-Gate Flash Memory Bitlines 3. A high electric field is created at 0V VDD Figure 4. Current 3 ...
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... Freescale Semiconductor, Inc. AN2400/D To erase the Flash, the sources and bitlines are connected to VSS (0V) and a high positive voltage (>>VDD) is applied to the control gate through the wordline, as illustrated in floating gate and the control gate. This causes Fowler-Nordheim tunnelling of electrons from the floating gate to the control gate, leaving the floating gate with a net positive charge ...
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... The EEPROM Clock Divider Register has identical bit definitions (bit names start with E instead of F). MOTOROLA For More Information On This Product PRDIV8 FDIV5 FDIV4 FDIV3 Figure 6. Flash Clock Divider Register (FCLKDIV) HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Split-Gate Flash Memory FDIV2 FDIV1 FDIV0 5 ...
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... Freescale Semiconductor, Inc. AN2400/D The command state machine requires a timebase that is derived from the microcontroller oscillator clock via a programmable prescaler. The oscillator is used as a clock source so that programming and erasure is independent of changes in the MCU bus frequency, in low power modes for example. The prescaler value is configured by the FCLKDIV register for Flash and the ECLKDIV register for EEPROM ...
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... PRDCLK=oscillator clock PRDCLK=oscillator clock/8 no PRDCLK[MHz]*(5+Tbus[µs]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) yes FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] ≥ 5 yes END AND FCLK ≥ 0.15MHz ? no yes FDIV[5:0] ≥ PROGRAM/ERASE IMPOSSIBLE HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Split-Gate Flash Memory 7 ...
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... Freescale Semiconductor, Inc. AN2400/D Flash Status Register 7 CBEIF NOTE: CBEIF, PVIOL and ACCER are cleared by writing a ‘1’ to the respective bit. CCIF, BLANK and bits 3, 1 and 0 are read only (write has no effect). The Flash Status register is banked on microcontrollers that have multiple Flash blocks ...
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... Erase Verify completion if the entire EEPROM block is erased. Program Program a word (2 bytes) 1 Sector Erase Erase a sector. Mass Erase Erase an entire block. 2 Sector Modify Erase a sector (4 bytes), program a word (2 bytes) HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Split-Gate Flash Memory Table 2. Valid Flash/EEPROM Description 9 ...
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... Freescale Semiconductor, Inc. AN2400/D Flash/EEPROM Command Sequence NOTE: A Flash or EEPROM word must be erased before it is programmed. The general command sequence begins with an initialisation sequence followed by the command write sequence. The initialisation sequence is described in the individual sections on Flash or EEPROM programming. If the CBEIF flag in the FSTAT/ESTAT register is set, the command write sequence can begin ...
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... CBEIF bit. Status Register Command Register $ Command State Machine Starting Control Figure 11. NVM Command Launch HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Split-Gate Flash Memory Commands. Address Buffer Data Buffer Address Data Address Register Data Register Empty Empty ...
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... Freescale Semiconductor, Inc. AN2400/D Status Register For pipelined operation, the next command sequence can begin as soon as the CBEIF bit is set. The command sequence is identical, beginning with the data write, followed by the command write and finally the command launch. Status Register Status Register ...
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... Running. Command Register Status Register $ Command State Machine Idle Control Figure 16. NVM Command Complete HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory Address Buffer Data Buffer Address+1 Data+1 Address Register Data Register Address Data Address Bus Data Bus ...
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... Freescale Semiconductor, Inc. AN2400/D The standard Flash block sizes are 32k bytes, 64k bytes and 128k bytes. A microcontroller may have a single Flash block of 32k, 64k or 128k bytes, or may have multiple blocks total of 512k bytes. Each Flash block can be programmed independently and simultaneously, thus enabling microcontroller programming times to be minimised ...
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... FCNFG register to select the bank of registers corresponding to the Flash block to be programmed, erased or verified. programmed if programming in the $8000 to $BFFF range. There is no need to set PPAGE if programming outwith this range the microcontroller does not have a page window. HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory Name ...
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... Freescale Semiconductor, Inc. AN2400/D Illegal Flash The ACCERR flag will be set during the command write sequence if any of the Operations following illegal operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing FCLKDIV the microcontroller has multiple Flash blocks, writing to the Flash 3 ...
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... The general procedure for programming multiple Flash blocks in parallel is shown in software has to supply the programming algorithm with data words for each Flash block in turn. MOTOROLA For More Information On This Product, enabled. Figure 17. Parallel Flash Block HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory Programming. The programming 17 ...
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... Freescale Semiconductor, Inc. AN2400/D 18 For More Information On This Product, Initialise FCLKDIV Verify that the PVIOL and ACCERR flags are clear for all combinations of the BLKSEL bits Write the BLKSEL bits in FCNFG to select next desired Flash block Programming $8000 - $BFFF for selected ...
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... Block 1 $C000 $30 $31 Flash Protected High Sectors $3F $E000 2K, 4K, 8K, 16K bytes $F000 $F800 $FF00 - $FF0F, Flash Protection/Security Field Figure 18. MC9S12DP256 Memory Map HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory $3B $3C $3D $3E $3F Block 0 $32 $33 $34 $35 $36 $37 Block 3 Block 2 19 ...
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... Freescale Semiconductor, Inc. AN2400/D NOTE: $30-$3F correspond to the PPAGE register content. Support for the paging mechanism is built into the HCS12 instruction set, with the CALL and RTC instructions. The CALL instruction is like the JSR instruction (jump to subroutine), but the CALL instruction automatically handles the PPAGE register to transfer control to a subroutine in paged memory ...
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... If the $A7 is read first, this will be interpreted as a NOP instruction and the next $18A7 will be read. MOTOROLA For More Information On This Product, HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory 21 ...
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... Freescale Semiconductor, Inc. AN2400/D Filling unused Flash with the op-code for the STOP instruction, $183E, does not give a good solution for two reasons. First, the STOP instruction is disabled by the ‘S’ bit in the CPU Condition Codes register. If the S bit is set, the STOP instruction is treated like a 2-cycle NOP and the microcontroller does not stop ...
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... Trying to program or erase any of the protected areas will result in a protection violation error and bit PVIOL will be set in the Flash Status Register FSTAT. A mass erase of an entire Flash block is only possible if protection of that block is fully disabled. MOTOROLA For More Information On This Product, HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory 23 ...
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... Freescale Semiconductor, Inc. AN2400/D 24 For More Information On This Product, $4000 Flash Block 0 protected $47FF low areas $4FFF $8000 $3D $3C $3E PPAGE = $C000 Flash Block 0 protected $E000 high areas $F000 $F800 Flash Protection/Security Field $FFFF Figure 19. 64k Flash Block 0 Protection Areas HCS12 NVM Guidelines Go to: www ...
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... For More Information On This Product NV6 FPHDIS FPHS1 FPHS0 Figure 20. Flash Protection Register (FPROT) Table 5. Flash Protection High Bits summarize the combinations of the HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory FPLDIS FPLS1 FPLS0 Table 4. Flash lists these and 25 ...
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... Freescale Semiconductor, Inc. AN2400/D FPOPEN — Flash Protection Open 1 = The Flash block protection depends on the FPHDIS, FPHS[1:0 The entire Flash block is protected against programming and erasure. NOTE: On some microcontrollers, the FPHDIS, FPHS[1:0], FPLDIS and FPLS[1:0] bits do have an effect on the selection of the protected Flash areas when FPOPEN = 0. Refer to the relevant Flash Block Guide for details. FPHDIS — ...
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... Flash blocks, the ACCERR and PVIOL flags in all other blocks must be clear and the BKSEL bits in the FCNFG register must be MOTOROLA For More Information On This Product, Definitions), the centre column contains equivalent assembly code HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory Appendix A ‘C’ 27 ...
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... Freescale Semiconductor, Inc. AN2400/D written to select the desired block for programming. This code snippet will not program over page boundaries. Registers: X contains first word aligned Flash address to be programmed, Y contains address of first word of data. Stack Pointer Stack Pointer + 2 C function local variables: UINT16* progAddr, UINT16* dataAddr, UINT16 wordsToDo ...
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... BRSET $105,#$30,fesef Command failed if either error flag set BRCLR $105,#$40,*+0 Wait for command to finish: this is optional, but the Flash block cannot be accessed until CCIF is set. CLRB Successful, return BRA fesertn fesef: Fail, return LDAB #1 fesertn: RTS HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory Parallel Flash Block 29 ...
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... Freescale Semiconductor, Inc. AN2400/D The leftmost column contains C code (variable definitions in Variable assuming the register base address is $0000, and the rightmost column contains comments. Prerequisites: FCLKDIV must be configured correctly, the flash block to be erased must not be protected, the Flash address must be word aligned (bit ...
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... BRSET $105,#$30,feevf Command failed if either error flag set BRCLR $105,#$40,*+0 Wait for command to finish: the BLANK bit is not valid until CCIF is set. BRCLR $105,#$04,feevf Check BLANK bit CLRB Successful, return BRA feevrtn feevf: Fail, return LDAB #1 feevrtn: RTS HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Flash Memory 31 ...
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... Freescale Semiconductor, Inc. AN2400/D EEPROM Introduction Most HCS12 microcontrollers also incorporate EEPROM that may be used to store data variables. HCS12 microcontrollers that do not have EEPROM may use Flash to emulate EEPROM, refer to application note AN2302/D for details and example software. The EEPROM on HCS12 microcontrollers is constructed using the same basic technology as the Flash memory, but with some adjustments to make it more suitable to data storage applications ...
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... EEPROM address space. previously written command. after writing to the command register, ECMD. command is in progress, the command is aborted and any pending command is aborted. HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D EEPROM Flash/EEPROM Command must be preceded with the 33 ...
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... Freescale Semiconductor, Inc. AN2400/D The PVIOL flag will be set during the command write sequence after the word write to the EEPROM address space and the command sequence will be aborted if any of the following illegal operations are performed. 1. Writing a EEPROM address to program in a protected area of the 2 ...
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... The erased state of these EEPROM memory bytes is $FF, which corresponds to EEPROM protection disabled. MOTOROLA For More Information On This Product NV6 NV5 NV4 EPDIS Figure 22. EEPROM Protection Register (EPROT) HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D EEPROM EP2 EP1 EP0 35 ...
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... Freescale Semiconductor, Inc. AN2400/D The EPOPEN bit in the EPROT register determines whether the entire EEPROM block is protected. When the EPOPEN bit is erased, the remainder of the bits in the register determine the state of protection and the size of the protected block. When the EPOPEN bit is programmed the entire EEPROM block is protected and the state of the remaining bits within the EPROT register is irrelevant ...
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... BRSET $115,#$30,eepwf Command failed if either error flag set BRCLR $115,#$40,*+0 Wait for command to finish: this is optional, but the EEPROM cannot be accessed until CCIF is set. CLRB Successful, return BRA eepwrtn eepwf: Fail, return LDAB #1 eepwrtn: RTS HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D EEPROM Appendix A ‘C’ 37 ...
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... Freescale Semiconductor, Inc. AN2400/D EEPROM Sector The following code segment demonstrates how to erase a sector (4 bytes) of Erase Command EEPROM. The leftmost column contains C code (variable definitions in Variable assuming the register base address is $0000, and the rightmost column contains comments. Prerequisites: ECLKDIV must be configured correctly, the sector to be erased must not be protected, the EEPROM address must be word aligned (bit ...
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... EEPROM cannot be accessed until CCIF is set. CLRB Successful, return BRA eemertn eemef: Fail, return LDAB #1 eemertn: RTS Definitions), the centre column contains equivalent assembly code HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D EEPROM Appendix A ‘C’ Appendix A ‘C’ 39 ...
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... Freescale Semiconductor, Inc. AN2400/D Registers: X contains any word aligned EEPROM address. Stack Pointer C function local variables: UINT16* eepromAddr, UINT16 dummy. On return, accumulator B contains 0 if the command executed correctly and the EEPROM verified as erased the command failed or the EEPROM was not erased. ...
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... BRSET $115,#$30,eesmf Command failed if either error flag set BRCLR $115,#$40,*+0 Wait for command to finish: this is optional, but the EEPROM cannot be accessed until CCIF is set. CLRB Successful, return BRA eesmrtn eesmf: Fail, return LDAB #1 eesmrtn: RTS HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D EEPROM 41 ...
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... Freescale Semiconductor, Inc. AN2400/D NVM Security HCS12 microcontrollers offer a memory security feature. This security feature is designed to prevent unauthorised access to the non-volatile memory. Note that memory security is not the same as memory protection, which is designed to prevent accidental modification of the NVM and is discussed in section ...
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... External access to internal Flash and EEPROM is disabled. Internal visibility (IVIS) and CPU pipe (IPIPE) information is disabled. Flash and EEPROM commands cannot be executed from external memory in Normal Expanded mode. HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D NVM Security Description Secured Secured Unsecured Secured ...
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... Freescale Semiconductor, Inc. AN2400/D Unsecuring the When secure, the microcontroller can be unsecured by one of the following Microcontroller methods. Backdoor Key Access In Normal modes (Single Chip and Expanded), security can be temporarily disabled by means of the Backdoor Key access method. This method requires that: • ...
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... That security is first disabled using the Backdoor Key method, allowing BDM to be used to issue commands to erase and program the Flash Options/Security byte, and The Flash sector containing the Flash Options/Security byte is not protected. HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D NVM Security 45 ...
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... Freescale Semiconductor, Inc. AN2400/D 7. Write $41 (Mass Erase) to the ECMD register. 8. Write $80 to the ESTAT register to clear CBEIF. 9. Write an appropriate value to the FCLKDIV register for correct timing. 10. Write $00 to the FCNFG register to select Flash block 0. 11. Write $10 to the FTSTMOD register ($0102) to set the WRALL bit, so the 12 ...
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... FCMD @(REG_BASE + 0x106); ESTAT @(REG_BASE + 0x115); ECMD @(REG_BASE + 0x116); HCS12 NVM Guidelines Go to: www.freescale.com AN2400/D Appendix A ‘C’ Variable Definitions /*function return values */ /*register base address */ /*FSTAT/ESTAT bit masks */ /*FCMD/ECMD commands*/ /*basic types */ /*MCU register types */ /*not used */ /*blank verify flag */ ...
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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 AN2400/D Go to: www.freescale.com ...