CY2XP24 Cypress Semiconductor, CY2XP24 Datasheet - Page 11

• Manufacturer Part Number: CY2XP24
• Description: Crystal to LVPECL Clock Generator
• Manufacturer: Cypress Semiconductor

Document History Page
Document #: 001-15705 Rev. *G
Document Title: CY2XP24 Crystal to LVPECL Clock Generator
Document Number: 001-15705
Rev.
*C
*D
*G
*A
*B
*E
*F
**
ECN No.
1285703
1451704
2669117
2700242
2718433
2767308
2896121
3218841
Submission
03/05/2009
04/30/2009
06/12/2009
09/22/2009
03/19/2010
03/07/2011
See ECN
See ECN
Date
WWZ/AESA Added I-temp devices
WWZ/KVM/
KVM/AESA Changed crystal frequency and output frequencies
KVM/PYRS Typos: changed VCC to VDD, changed ps to MHz
WWZ/HMT No change. Submit to ECN for product launch.
Change
Orig. of
BASH
KVM
KVM
ARI
New data sheet
Updated phase jitter value
Rise & fall times changed from 350 ps to 500 ps (typ.)
Junction temperature changed from 125C to 135C
Changed IIL and IIH values
Entered value for IDD
Removed MSL spec
Changed Data Sheet Status to Final
Changed footnote about external power dissipation
Reformatted AC and DC tables
Changed LVPECL parameters from VPP to VOD and VOCM
Added CINX spec
Added IDD for 2.5V
Added TLOCK timing
Revised text in Application Information section
Changed recommended crystal load capacitor values
Add phase jitter spec for 12 kHz - 20 MHz integration range
Add I
Change parameter name for I
Remove I
Add footnote reference to C
Add max limit for T
Change T
Split out parameter T
Updated Package Diagram (Figure 11)
Updated as per template
Added Acronyms and Units of Measure table
Added Ordering Code Definition details
Updated package diagram 51-85093 from *B to *C
DD
spec for unterminated outputs
DD
LOCK
footnote about externally dissipated current
max from 10 ms to 5 ms
R
, T
LFS
F
: 1.0 ns
from T
Description of Change
IN
DD
and C
LOCK
(terminated outputs) from I
INX
:not 100% tested
DD
CY2XP24
to I
Page 11 of 12
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