AN2372 Freescale Semiconductor / Motorola, AN2372 Datasheet - Page 18

• Manufacturer Part Number: AN2372
• Description: Using the Output Compare TPU Function (OC) with the MPC500Family
• Manufacturer: Freescale Semiconductor / Motorola

State 1: HOST_MATCH (Host-Initiated Pulse Mode)
size. TPU microcode source listings for all functions in the TPU function library can be downloaded from
the Motorola Freeware bulletin board. Refer to Using the TPU Function Library and TPU Emulation Mode
(TPUPN00/D) for detailed instructions on downloading and compiling microcode.
The output compare function consists of five states, described below. The host-initiated pulse mode of
operation uses states 1 and 2, and the continuous pulse mode of operation uses states 3 through 5.
For clarity, reference is made to internal channel flags in the following descriptions. These internal TPU
control bits are not available to the user. The channel flags, flag1 and flag0, indicate the mode of operation
or direct the function to execute a routine. Flag0 is set during initialization of the continuous pulse mode
and defines the current mode of operation. When set, the continuous pulse mode is operating. When clear,
the host-initiated pulse mode is operating. Flag1 is set during initialization of the continuous pulse mode to
implement a one-time execution after initialization of a microcode sequence in Offset_Cal.
9.1
This state is entered to initialize the host-initiated pulse mode as a result of an HSR %01. Parameter RAM
word locations 0xEC and 0xEE are updated with the most recent TCR1 and TCR2 values, respectively.
If host sequence bit 1 is one, an interrupt is asserted to the CPU and execution ends. If host sequence bit 1
is zero, match and input transition service requests are enabled, and the channel is configured to generate a
match event at the new time. A new match time value is calculated, and the event register and REF_TIME
are updated with the new desired match value (OFFSET plus (REF_ADDR1)). The channel is programmed
to specify the pin direction, the time base for comparison, the initial pin state, and the desired pin action on
a match event as specified by CHANNEL_CONTROL. Flag0 and flag1 are cleared.
Condition: HSR1, HSR0, M/TSR, LSR, Pin, Flag0 = 11xxxx
Match Enable: Don't Care
Configure channel latches via parameter CHANNEL_CONTROL
Enable M/TSR
Assert flag0, assert flag1
ACTUAL_MATCH_TIME = ERT
Negate MRL, TDL, LSR
Assert interrupt request
9.2
In the host-initiated pulse mode, this state is entered as a result of a match event with flag0 equal to zero.
An interrupt is generated, signaling the CPU that the previously configured match occurred and that a new
match may be configured. The time of the match event is stored in ACTUAL_MATCH_TIME.
Condition: HSR1, HSR0, M/TSR, LSR, Pin, Flag0 = 00x1x1 Match Enable: Don't Care
Configure channel latches via parameter CHANNEL_CONTROL REF_TIME replaced by (REF_ADDR1)
If (channel flag1 = 1) then {
/* if first link after initialization: get a reference time and put in ERT */ REF_TIME replaced by
(REF_ADDR3)
18
State 1: HOST_MATCH (Host-Initiated
Pulse Mode)
State 2: Ref_Time_Match
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