CY2SSTV857-32 Cypress Semiconductor, CY2SSTV857-32 Datasheet

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... In addition, the CY2SSTV857-32 features differential feedback clock outpts and inputs. This allows the CY2SSTV857- used as a zero delay buffer. When used as a zero delay buffer in nested clock trees, the CY2SSTV857-32 locks onto the input reference and translates with near-zero delay to low-skew outputs ...

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... Power Supply for Output Clock Buffers. 2.6V Nominal AVDD 2.6V Power Supply for PLL. When VDDA is at GND, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (PD# = 0), the PLL is powered down. VSS Common Ground. AVSS Analog Ground. CY2SSTV857- VDDQ 28 PD# 27 ...

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... Zero Delay Buffer When used as a zero delay buffer the CY2SSTV857-32 will likely nested clock tree application. For these applica- tions, the CY2SSTV857-32 offers a differential clock input pair as a PLL reference. The CY2SSTV857-32 then can lock onto the reference and translate with near zero delay to low-skew outputs ...

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... Figure 2. Propagation Delay Time C(n) Figure 3. Cycle-to-cycle Jitter PLL 120 Ohm FBIN 120 Ohm FBIN# FBOUT FBOUT# Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< Figure 4. Clock Structure # 1 CY2SSTV857- PLH PHL t C(n+1) = 2.5" = 0.6" (Split to Terminator) DDR - SDRAM VTR VCP DDR - SDRAM 0.3" 120 ...

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... PLL 120 Ohm FBIN 120 Ohm FBIN# FBOUT FBOUT# Figure 5. Clock Structure # Figure 6. Differential Signal Using Direct Termination Resistor CY2SSTV857-32 = 2.5" = 0.6" (Split to Terminator) DDR-SDRAM DDR-SDRAM DDR-SDRAM VTR VCP DDR-SDRAM DDR-SDRAM DDR-SDRAM 0.3" ...

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... PD and CLK/CLK MHz [9, 10] Description MHz to 100 MHz 101 MHz to 170 MHz 20%–80% of VOD [12] (all outputs) [12] (all outputs) and is the voltage at which the differential signal must be crossing. DDQ CY2SSTV857-32 and V should be constrained to the in out < < out DDQ DDQ Min ...

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... TSSOP–Tape and Reel 40-pin QFN 40-pin QFN–Tape and Reel 48-pin TSSOP 48-pin TSSOP–Tape and Reel 857-32 Marketing Part Number 0327L11 Date Code and Fab Location *SWR# Lot Code Figure 7. Actual Marking on the Device CY2SSTV857-32 Condition Min. Typ. –75 – –100 – 1.5 3.5 1.5 3.5 – ...

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... C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.30[0.012] 0.50[0.020] 0°-12° C SEATING PLANE CY2SSTV857-32 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 0.508[0.020] 0.762[0.030] 0°-8° 0.100[0.003] ...

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... Document History Page Document Title: CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant Document Number: 38-07557 REV. ECN No. Issue Date ** 128403 08/04/03 *A 129080 09/05/03 *B 130114 10/28/03 *C 210076 See ECN *D 259010 See ECN *E 308437 See ECN www.DataSheet4U.com Document #: 38-07557 Rev. *E Orig. of Change Description of Change RGL New Data Sheet ...