CY2SSTV850 Cypress Semiconductor, CY2SSTV850 Datasheet - Page 6

• Manufacturer Part Number: CY2SSTV850
• Description: Differential Clock Buffer/Driver
• Manufacturer: Cypress Semiconductor

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AC Parameters
Note:
Document #: 38-07457 Rev. *A
11. Parameters are guaranteed by design and characterization. Not 100% tested in production.
12. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
13. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
14. Refers to transition of non-inverting output.
15. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
16. All differential input and output terminals are terminated with 120 /16 pF as shown in Figure 6.
17. DUT refers to Device Under Test.
f
t
t
t
tp
tp
t
t
t
t
t
t
t
d(0)
CLK
DC
lock
R
CCJ
t
PLH
PHL
SK(0)
PHASE
JITT(PHASE)
jit(h-per)
/t
ZL
LZ
Parameter
F
spread of –0.5%.
where the cycle time (t
, tp
, tp
ZH
HZ
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time
(all outputs)
Output Disable Time
(all outputs)
Cycle to Cycle Jitter
Half-period jitter
Low-to-High Propagation Delay,
CLKINT to YT[0:9]
High-to-Low Propagation Delay,
CLKINT to YT[0:9]
Any Output to Any Output Skew
Phase Error
Phase Error Jitter
Dynamic Phase Offset
[11, 12]
C
) decreases as the frequency goes up.
(V
DD
[16]
= V
Description
DDQ
[15]
[14]
[14]
= 2.5V±5%, V
[13]
[16]
DDI
= 3.3V±5%, T
A
20% to 80% of VOD
f > 66 MHz
f > 66 MHz
f > 66 MHz
CLKIN pins to FBIN pins at the
DUT
VDD
[17]
, V
DD
Conditions
A
= 2.5V ± 0.2V
= 0°C to +70°C)
–100
–100
–150
Min.
–50
1.5
1.5
60
40
30
1
Typ.
3.5
3.5
CY2SSTV850
3
3
Max.
170
100
100
100
100
150
140
60
50
2
6
6
Page 6 of 11
MHz
Unit
V/ns
WH
ns
ns
ps
ps
ns
ns
ps
ps
ps
ps
%
s
/t
C
,