CY2SSTV850 Cypress Semiconductor, CY2SSTV850 Datasheet
CY2SSTV850
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CY2SSTV850 Summary of contents
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... Serial YC3 Interface YT4 Logic YC4 YT5 YC5 YT6 YC6 YT7 YC7 PLL YT8 YC8 YT9 YC9 FBOUTT FBOUTC • 3901 North First Street CY2SSTV850 Pin Configuration VSS 1 48 VSS 2 47 YC5 YC0 3 46 YT5 YT0 4 45 VDDQ VDDQ 5 44 YT6 ...
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... Supply for Logic 2.5V Power Supply for Output Clock Buffers 2.5V Nominal 2.5V Power Supply for PLL Power Supply for two-line serial Interface Common Ground Analog Ground CY2SSTV850 Electrical Characteristics LV Differential Input Differential Input Differential Outputs Differential Outputs Data Input for the two-line serial ...
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... When used as a zero-delay buffer the CY2SSTV850 will likely nested clock tree application. For these applications the CY2SSTV850 offers a differential clock input pair as a PLL reference. The CY2SSTV850 then can lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback input, FBINT, is con- nected to the feedback output, FBOUTT ...
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... SDATA hold time H(SDATA) t STOP set-up time SU(STOP) www.DataSheet4U.com Document #: 38-07457 Rev bit 1 bit 8 bits R/W Ack Command Code Data Byte 1 Ack Ack 1 bit 8 bits 1 bit Description CY2SSTV850 1 bit 8 bits Ack Byte Count N ..... Byte Byte N Stop Ack 8 bits 1 bit 1 bit Min. Max. 100 4.7 4.7 4.0 4.7 4.0 ...
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... VTR is the true input level and VCP is the complementary TR CP and is the voltage at which the differential signals must be crossing. DDQ + V |/2. In case of each clock directly terminated by a 120 resistor. See Figure CY2SSTV850 and V should be constrained to the in out < < ...
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... V = 3.3V±5%, T DDQ DDI Description VDD DD [13] 20% to 80% of VOD [14] [14] f > 66 MHz [15] f > 66 MHz [16] [16] f > 66 MHz CLKIN pins to FBIN pins at the [17] DUT CY2SSTV850 = 0°C to +70°C) A Conditions Min. Typ. = 2.5V ± 0. –100 –100 1.5 3.5 1.5 3.5 –150 –50 30 Max. ...
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... CLKINC FBINT FBINC www.DataSheet4U.com YT[0:9], FBOUTT YC[0:9], FBOUTC YT[0:9], FBOUTT YC[0:9], FBOUTC Document #: 38-07457 Rev large number of samples Figure 1. Static Phase Offset Figure 2. Dynamic Phase Offset tsk(o) Figure 3. Output Skew CY2SSTV850 Page ...
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... Figure 4. Half-Period Jitter t c( it(cc) Figure 5. Cycle-to-Cycle Jitter CY2SSTV850 t (hper_N+ c(n) -t c(n) c(n+ Page ...
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... Document #: 38-07457 Rev. *A Package Type 48-pin SSOP 48-pin SSOP - Tape and Reel 48-pin TSSOP 48-pin TSSOP - Tape and Reel 48-Lead Shrunk Small Outline Package O48 CY2SSTV850 Product Flow Commercial Commercial Commercial Commercial 51-85061-*C ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. (continued) CY2SSTV850 51-85059-*B Page ...
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... Revision History Document Title: CY2SSTV850 Differential Clock Buffer/Driver Document #: 38-07457 Rev. *A Issue REV. ECN NO. Date ** 117540 09/09/02 *A 122933 12/18/02 www.DataSheet4U.com Document #: 38-07457 Rev. *A Orig. of Change Description of Change HWT New data sheet RBI Add power up requirements to maximum ratings information CY2SSTV850 Page ...