CY2SSTU877 Cypress Semiconductor, CY2SSTU877 Datasheet - Page 4

• Manufacturer Part Number: CY2SSTU877
• Description: 10-Output JEDEC-Compliant Zero Delay Buffer
• Manufacturer: Cypress Semiconductor

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Document #: 38-07575 Rev. *B
Tjit (H-Period)
T
T
T
T
T
T
T
T
AC Timing Specifications
d(0)
d(0)
SKEW
R
ODC
OENB
ODIS
PLH
/T
Parameter
F
Half Period Cycle-to-cycle jitter
Static Phase Offset
Dynamic Phase Offset
Clock Skew
Rise/Fall Time
Output Duty Cycle
Output Enable Time
Output Disable Time
Propagation Delay
Description
(continued)
Figure 1. Test Loads for Timing Measurement #1
Figure 2. Test Loads for Timing Measurement #2
PRELIMINARY
Above 270 MHz
Below 270 MHz
Average 1000 cycles
(Y[0:9], Y#[0:9] @ 500 MHz)
OE to any Y/Y#
OE to any Y/Y#
Conditions
Min.
–45
–70
–50
–30
49
–
–
–
–
CY2SSTU877
8
Max.
300
45
70
50
30
25
51
8
8
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Unit
ps
ps
ps
ps
ps
ps
ns
ns
ns
%