CY2SSTU877 Cypress Semiconductor, CY2SSTU877 Datasheet - Page 2

• Manufacturer Part Number: CY2SSTU877
• Description: 10-Output JEDEC-Compliant Zero Delay Buffer
• Manufacturer: Cypress Semiconductor

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Document #: 38-07575 Rev. *B
Pin Description
Table 1. Function Table
Recommended Operating Conditions
G1
H1
E1, F1
E6, F6
H6, G6
B2, B3, B4, B5, C2,
C5, H2, H5, J2, J3,
J4, J5
F5
D5
D2, D3, D4, E2, E5,
F2, G2, G3, G4, G5
A2, A1, D1, J1, K3,
A5, A6, D6, J6, K4,
A3, B1, C1, K1, K2,
A4, B6, C6, K6, K5
T
T
V
Parameter
A
A
DD
AVDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
(Ind.)
(Com.)
X
(BGA)
Ambient Operating Temp
Ambient Operating Temp
Operating Voltage
OE
H
H
H
H
L
L
L
X
X
L
Pin No.
7
8
4, 5
27, 26
24, 25
10
22
21
1, 6, 9, 15, 20, 23, 28,
31, 36
38, 39, 3, 11, 14, 34,
33, 29, 19, 16
37, 40, 2, 12, 13, 35,
32, 30, 18, 17
Inputs
OS
X
X
H
H
X
X
X
X
L
L
Description
QFN
CLK
H
H
H
H
H
L
L
L
L
L
CLK#
AGND
AVDD
CLK, CLK#
FBOUT, FBOUT#
GND
OE
OS
VDDQ
Y [0:9]
Y# [0:9]
FBIN, FBIN#
H
H
H
H
H
L
L
L
L
L
PRELIMINARY
Name
Lz,Y7 Active
Lz,Y7 Active
Lz
Lz
Lz
Y
H
H
L
L
Condition
Ground for 1.8V analog supply
1.8V analog supply
Differential clock input with a (10K–100KΩ) pull-down resistor
Feedback differential clock input
Feedback differential clock output
Ground
Output enable (ASYNC) for Y[0:9] and Y# [0:9]
Output Select (Tied to GND or VCC)
1.8V supply
Buffered output of input clock, CLK
Buffered output of input clock, CLK
Lz,Y7# Active
Lz,Y7# Active
Y#
Lz
Lz
Lz
H
H
L
L
Outputs
Reserved
FBOUT
Description
Lz
Min.
–40
H
H
H
H
L
L
L
L
1.7
0
FBOUT#
CY2SSTU877
Lz
H
H
H
H
L
L
L
L
Max.
1.9
85
70
Bypassed/Off
Bypassed/Off
Bypassed/Off
Bypassed/Off
Page 2 of 9
PLL
On
On
On
On
Off
Unit
°C
°C
V