AN2269 Freescale Semiconductor / Motorola, AN2269 Datasheet - Page 3

• Manufacturer Part Number: AN2269
• Description: Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus
• Manufacturer: Freescale Semiconductor / Motorola

1.3 Device Inter-Operation
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2.1 Host Memory Controller
2.2 HDI16 Host Interface
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For details on these MPC8260 modules, consult the MPC8260 PowerQUICC II User’s Manual: Chapter 10 (memory
controller) and 18 (SDMA Channels and IDMA Emulation). For details on these MSC8101 modules, consult the
MSC8101 Reference Manual: Chapter 14 (HDI16), Chapter 10 (memory controller), and Chapter 15 (DMA). For details
on programming the HDI16 port and the DMA controller, consult the MSC8101 User’s Guide.
System Bus–HDI16 Host Interface
• Multi-channel DMA Controller. Supports up to 16 time-division multiplexed channels and buffer
The host MPC8260 device must configure its memory controller to map the HDI16 host-side registers
into memory locations within its 60x system bus memory space. The HDI16 MSC8101 device configures
the HDI16 directly, treating it as an internal peripheral. After initial set-up of the HDI16 host interface,
the communication between the host MPC8260 device and the HDI16 MSC8101 device occurs via DMA
transfers, which are automatically triggered by signals generated from the HDI16 host interface. This
application note describes how to configure and use the MPC8260 memory controller and IDMA module
as well as the MSC8101 HDI16 host interface and DMA controller.
To understand the function of the parallel control interface between the host MPC8260 system bus and
the HDI16 MSC8101 host interface, it is important to know the device requirements on each side.
The SDRAM machine provides an interface to synchronous DRAMs, using SDRAM pipelining, bank
interleaving, and back-to-back page mode to achieve the highest performance. The GPCM provides
interfacing for simpler, lower-performance memory resources and memory-mapped devices. The GPCM
has inherently lower performance because it does not support bursting. GPCM-controlled banks are used
primarily for boot loading and access to low-performance memory-mapped peripherals. The UPM
supports address multiplexing of the external bus, refresh timers, and generation of programmable
control signals for row and column address strobes to allow for a glueless interface to DRAMs, burstable
SRAMs, and almost any kind of peripheral. The refresh timers allow refresh cycles to be initiated. The
UPM can generate different timing patterns for the control signals that govern a memory device. These
patterns define how the external control signals behave during a read, write, burst-read, or burst- write
access request. Refresh timers are also available to generate user-defined refresh cycles periodically. We
selected the UPM as the most suitable interface for the application discussed in this document.
The HDI16 host interface has two sets of 16-bit wide registers, one set visible only within the MSC8101
and the other set visible only to the external host processor (see Figure 2). All HDI16 registers are
mapped directly onto the MSC8101 QBus, and the transmit and receive FIFOs are mapped onto the DMA
data bus so that the DMA controller can access them directly without intervention by the SC140 core.
The QBus, which is part of the SC140 extended core interface, is a high-speed pipeline bus with separate
address and data phases. It is a single-master bus with the same frequency as the SC140 core. The
MSC8101 peripherals, in particular the HDI16 interface, are slaves to the QBus.
alignment by hardware. The DMA controller connects to both the system bus and the local bus and can
function as a bridge between both buses. The DMA controller enables hot swap between channels
using time-division multiplexed channels that impose no cost in clock cycles. Sixteen priority levels
support synchronous/synchronous transfers on the bus and give a varying bus bandwidth per channel.
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
System Bus–HDI16 Host Interface
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