AN2269 Freescale Semiconductor / Motorola, AN2269 Datasheet - Page 13

• Manufacturer Part Number: AN2269
• Description: Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus
• Manufacturer: Freescale Semiconductor / Motorola

4.3.2 DPR Parameters
The BD associated with IDMA Channel 2 (Host Rx) is configured with the following parameters:
• Valid. The BD contains valid data for transfer to be processed.
• Wrap. This is the last BD in the BD table; wrap back to the BD at the base of the table once the current
• Interrupt. Once the buffer is processed, set a bit in the IDSR register (which we can use to generate a
• Last. This is the last buffer in the chain; terminate the current IDMA transfer after it is processed.
• Continuous mode. Do not clear the Valid bit after this buffer is processed so that the data within it is
• Destination byte ordering is Big Endian.
• Destination address is on the local bus.
• Source byte ordering is Big Endian.
• Source address is on the 60x bus.
• Data length is 32 bytes (one burst).
• Source buffer pointer. Points to 32-byte aligned location of the HDI16 Rx 0 Host Register.
• Destination buffer pointer. Points to 32-byte aligned location in SDRAM at which to store the received
These BD settings enable 32-byte burst and 64-bit transfers to be performed continuously by issuing the
START_IDMA command associated with a particular IDMA channel, without updating the BD
parameters.
IDMA Channel 1 (host Tx) DPR parameters are configured as follows:
• Dual Address mode. The data read from the source address is stored in DPR and then transferred from
• Set SINC. Source address pointer is incremented by the number of bytes transferred in the source read
• Set DINC: Destination address pointer is incremented by the number of bytes transferred in the source
• ERM: Trigger IDMA upon
• S/D: Read from memory, write to memory (the HDI16 appears as memory to the host).
• SS_MAX: Maximum transfer size is 32 bytes.
• STS: Source transfer size is 32 bytes.
• DTS: Destination transfer size is 8 bytes.
IDMA Channel 2 (host Rx) DPR parameters are configured as follows:
• Dual Address mode. The data read from the source address is stored in DPR and then transferred from
• Set SINC: Increments the source address pointer by the number of bytes transferred in the source read
• Set DINC. Destination address pointer is incremented by the number of bytes transferred in the source
one is processed. Our application uses only one BD, so it wraps back to itself.
core interrupt, if desired).
still valid when we issue the START_IDMA command again.
pattern.
DPR to the destination; that is, it is a two-step process. The interim storage location in DPR is specified
by DPR_BUF.
transaction.
read transaction.
DPR to the destination in a two-step process. DPR_BUF specifies the interim storage location in DPR.
transaction.
read transaction.
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DREQ
assertion
Host Device Configuration
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