AN2269 Freescale Semiconductor / Motorola, AN2269 Datasheet - Page 10

• Manufacturer Part Number: AN2269
• Description: Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus
• Manufacturer: Freescale Semiconductor / Motorola

Host Device Configuration
3.2.3 DMA Interrupts
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Host Device Configuration
Tx Complete
external memory or an internal peripheral and internal memory. The HDI16 MSC8101treats the HDI16
interface is an internal peripheral, making it easy to transfer data to and from the HDI16 interface and
internal memory.
The HDI16 MSC8101 DMA controller services both transmit and receive data registers for data transfers.
To set up the DMA interrupt vector appropriately in the vector table, all interrupts must be disabled. The
IRQ18 vector is called each time a DMA interrupt is triggered by a “buffer terminated” event. A handler
must be attached to this vector to handle the interrupts.
DMA servicing is divided into two parts in the interrupt handler: read/receive and write/transmit. Each
routine is assigned to a given channel. In this application, DMA channel 0 and 1 are programmed
respectively to perform DMA read and DMA write routines, using DMA Channel Configuration registers
(DCHCRx) to configure the connection between a DMA requestor and the corresponding DMA channel.
All the channel properties are programmed, including the relevant lines in DCPRAM, before the channel
is enabled by asserting the ACTV bit.
The first task of the interrupt routines is to clear pending requests by writing to the Interrupt Pending
registers (IPRx). The PIC interrupt pending registers, IPRA and IPRB, are 16-bit read/write registers that
the SC140 core uses to monitor pending interrupts and to reset edge-triggered interrupts. The DMA
controller reports status and events to the host, and it generates a maskable interrupt for each channel.
The maskable interrupt is routed to the PIC according to the setting of the M bit of the relevant channel in
the DMA Internal Mask Register (DIMR). By reading the DMA Status Register (DSTR), we can check
which channel has requested use of the DMA controller.
When the
For an HDI16 read request, a DMA transfer extracts data for the host receive FIFO and writes to a data
buffer in memory. In contrast, if an HDI16 write request is received, a DMA transfer occurs between the
data buffer in memory and the HDI16 host transmit FIFO.
The operation of the external host is illustrated in its most basic form in the state transition diagram
shown in Figure 4.
Transmitting Data
IRQ
Figure 4. Simple Representation of Host States
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servicing routine is called, a special type of DMA transfer starts, depending on the request.
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Tx Request
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Awaiting Core Request
Initializing
Initialization Complete
Rx Request
Receiving Data
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