CY29948 Cypress Semiconductor, CY29948 Datasheet - Page 3

• Manufacturer Part Number: CY29948
• Description: 1:12 Clock Distribution Buffer
• Manufacturer: Cypress Semiconductor

Maximum Ratings
Maximum Input Voltage Relative to V
Maximum Input Voltage Relative to V
Storage Temperature ............................... –65 °C to + 150 °C
Operating Temperature............................... –40 °C to +85 °C
Maximum ESD protection............................................... 2 kV
Maximum Power Supply................................................ 5.5 V
Maximum Input Current ............................................. ±20 mA
DC Parameters
V
Document Number: 38-07288 Rev. *E
V
V
I
I
V
V
V
V
I
I
Z
C
Notes
IL
IH
DDQ
DD
Parameter
DD
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The V
5. Driving series or parallel terminated 50  (or 50  to V
IL
IH
PP
CMR
OL
OH
out
in
and the input lies within the V
= V
DDC
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V
= 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range.
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Dynamic Supply Current
Output Impedance
Input Capacitance
Description
[2]
PP
specification.
[3]
[3]
[5]
[5]
SS
DD
[4]
............. V
............. V
V
V
All other inputs
V
V
All other inputs
V
V
I
I
I
V
C
V
C
V
C
V
C
V
V
OL
OH
OH
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
L
L
L
L
DD
= 30 pF
= 30 pF
= 30 pF
= 30 pF
= 20 mA
= –20 mA, V
= –20 mA, V
/2) transmission lines.
= 3.3 V, PECL_CLK single ended
= 2.5 V, PECL_CLK single ended
= 3.3 V, PECL_CLK single ended
= 2.5 V, PECL_CLK single ended
= 3.3 V
= 2.5 V
= 3.3 V, Outputs @ 100 MHz,
= 3.3 V, Outputs @ 160 MHz,
= 2.5 V, Outputs @ 100 MHz,
= 2.5 V, Outputs @ 160 MHz,
= 3.3 V
= 2.5 V
DD
SS
– 0.3 V
+ 0.3 V
Conditions
DD
DD
= 3.3 V
= 2.5 V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, V
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
< (V
in
or V
in
and V
out
) < V
V
V
DD
DD
out
2.135
1.49
1.10
1.75
Min
V
300
2.0
2.5
1.8
SS
12
14
DD
–
–
–
–
–
–
–
–
–
SS
– 2.0
– 1.2
should be constrained to the range:
or V
DD
).
Typ
180
270
125
190
15
18
–
–
–
–
–
–
–
–
–
–
–
–
–
5
4
–
V
V
DD
DD
1.825
–100
1000
Max
1.45
2.42
V
100
0.8
2.0
0.4
18
22
–
–
7
–
–
–
–
–
DD
– 0.6
– 0.6
CY29948
Page 3 of 10
Unit
mV
mA
mA
µA
CMR
pF
V
V
V
V
V

range
[+] Feedback