CY29948 Cypress Semiconductor, CY29948 Datasheet - Page 2

• Manufacturer Part Number: CY29948
• Description: 1:12 Clock Distribution Buffer
• Manufacturer: Cypress Semiconductor

Pin Description
Output Enable/Disable
The CY29948 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When
SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown
in
Document Number: 38-07288 Rev. *E
Note
17, 19, 21, 23,
10, 14, 18, 22,
25, 27, 29, 31
1. PD = Internal pull-down, PU = Internal pull-up.
8, 12, 16, 20,
9, 11, 13, 15,
Figure
24, 28, 32
26, 30
Pin
3
4
2
1
5
6
7
1.
SYNC_OE
TCLK
PECL_CLK#
PECL_CLK
TCLK_SEL
SYNC_OE
Q
Q(11:0)
VDDC
Name
TCLK
[1]
VDD
VSS
TS#
VDDC
PWR
–
–
–
–
–
–
–
–
–
Figure 1. SYNC_OE Timing Diagram
I, PU PECL Input Clock
I, PD PECL Input Clock
I, PU External Reference/Test Clock Input
I, PU Clock Select Input. When LOW, PECL clock is selected. When HIGH
I, PU Output Enable Input. When asserted HIGH, the outputs are enabled.
I, PU Three-state Control Input. When asserted LOW, the output buffers
I/O
O
–
–
–
Clock Outputs
TCLK is selected.
When set LOW the outputs are disabled in a LOW state.
are three-stated. When set HIGH, the output buffers are enabled.
2.5 V or 3.3 V Power Supply for Output Clock Buffers
2.5 V or 3.3 V Power Supply
Common Ground
Description
CY29948
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