CY28RS400 Cypress Semiconductor, CY28RS400 Datasheet - Page 5

• Manufacturer Part Number: CY28RS400
• Description: Clock Generator for ATI RS400 Chipset
• Manufacturer: Cypress Semiconductor

Document #: 38-07637 Rev. *B
Control Registers
Byte 0:Control Register 0
Byte 1: Control Register 1
Byte 2: Control Register 2
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
@Pup
@Pup
@Pup
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
SRCS[T/C]1
SRCS[T/C]0
SRC [T/C]0
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Reserved
Reserved
Reserved
USB_48
CPUT/C
SRCT/C
USB_48
Name
Name
Name
REF2
REF1
REF0
PCI0
CPU
SRC
PCI
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
REF2 Output Enable
0 = Disable, 1 = Enable
REF1 Output Enable
0 = Disable, 1 = Enable
REF0 Output Enable
0 = Disable, 1 = Enable
PCI0 Output Enable
0 = Disable, 1 = Enable
USB_48MHz Output Enable
0 = Disable, 1 = Enable
CPU[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Spread Spectrum Selection
‘0’ = -0.35%
‘1’ = -0.50%
48MHz Output Drive Strength
0 = 1x, 1 = 2x
33MHz Output Drive Strength
0 = 1x, 1 = 2x
Reserved
Reserved
CPU/SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Reserved
Description
Description
Description
CY28RS400
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