CY28RS400 Cypress Semiconductor, CY28RS400 Datasheet
CY28RS400
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CY28RS400 Summary of contents
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... VSS_SRC VDD_48 MHz SRCT4 SRCC4 SRCT3 USB_48 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1 • 3901 North First Street • San Jose CY28RS400 RS400 Chipset SRC PCI REF USB_48 VDD_REF 2 55 VSS_REF 3 54 REF0/FSA 4 ...
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... Ground for REF outputs GND Ground for SRC outputs GND Ground for SRC outputs GND Ground for SRCS outputs GND Analog Ground I 14.318-MHz Crystal Input O 14.318-MHz Crystal Output CY28RS400 Description Type-5 buffer. / CPU Frequency Select. Intel Type-5 buffer. Page ...
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... The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description Bit 1 8 18:11 19 CY28RS400 PCIF/PCI REF0 33 MHz 14.318 MHz 33 MHz 14.318 MHz 33 MHz 14.318 MHz 33 MHz 14.318 MHz 33 MHz 14 ...
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... Byte Read Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop CY28RS400 Page ...
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... CPUT/C Spread Spectrum Selection SRCT/C ‘0’ = -0.35% ‘1’ = -0.50% USB_48 48MHz Output Drive Strength PCI 33MHz Output Drive Strength Reserved Reserved CPU CPU/SRC Spread Spectrum Enable SRC 0 = Spread off Spread on Reserved CY28RS400 Description Description Description Page ...
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... SRC[T/C]1 free running SRC[T/C]0 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running Reserved Reserved Name SRC[T/C]5 CLKREQ#1 control 1 = SRC[T/C]5 stoppable by CLKREQ#1 pin 0 = SRC[T/C]5 free running SRC[T/C]4 CLKREQ#1 control 1 = SRC[T/C]4 stoppable by CLKREQ#1 pin 0 = SRC[T/C]4 free running CY28RS400 Description Description Description Description Page ...
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... FS_A Reflects the value of the FS_A pin sampled on power up FS_A was low during VTT_PWRGD# assertion. Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 CY28RS400 Description Description Description Page ...
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... Crystal Recommendations The CY28RS400 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS400 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. Figure 3. Power-down Assertion Timing Waveform CY28RS400 Page ...
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... CPU_STP Hi-Z bit corresponding to the output of interest is programmed to ‘1’, the final state of the stopped CPU clock is low (due to external 50 ohm pull-down resistor), both CPUT clock and CPUC clock outputs will not be driven. Figure 5. CPU_STP# Assertion Waveform Tdrive_CPU_STP#,10nS>200mV Figure 6. CPU_STP# Deassertion Waveform CY28RS400 Page ...
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... SRC outputs resuming simultaneously. If the CLKREQ# programmed to ‘1’ (three-state), the all stopped SRC outputs must be driven high within CLKREQ#[1:0] assertion to a voltage greater than 200 mV. CY28RS400 1.8mS 1.8mS drive mode bit is Page ...
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... Sample Sels Delay VTT_PW RGD# State 1 State 2 On Figure 10. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28RS400 Device is not affected, VTT_PW RGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
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... max load and frequency PD asserted, Outputs driven PD asserted, Outputs Hi-Z Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification CY28RS400 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0.5 V +0.5 ...
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... OH Determined as a fraction of 2*(T – T )/( Measured at crossing point Vox Math averages Figure 13 Math averages Figure 13 See Figure 13. Measure SE Measured at crossing point V Measured at crossing point V CY28RS400 Condition Min. 69.841 and DD – – – 9.997001 10.00300 ns OX 7.497751 7.502251 ...
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... Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V CY28RS400 Condition Min. 9.997001 10.05327 ns OX 10.12800 9.872001 9.872001 10.17827 ns – – OX – 0.175 to OL 175 – ...
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... Figure 12. Single-ended Load Configuration 3 3 Ω Ω Ω Ω Ω Ω Figure 13. 0.7V Load Configuration CY28RS400 Condition Min. 0.5 – – 10.0 0 Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF ...
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... SSOP – Tape and Reel CY28RS400ZC 56-pin TSSOP CY28RS400ZCT 56-pin TSSOP – Tape and Reel Lead-free CY28RS400OXC 56-pin SSOP CY28RS400OXCT 56-pin SSOP – Tape and Reel CY28RS400ZXC 56-pin TSSOP CY28RS400ZXCT 56-pin TSSOP – Tape and Reel Package Diagrams 28 29 0.720 0.730 0.088 ...
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... SEATING 0.279[0.011] PLANE 2 C system, provided that the system conforms to the I CY28RS400 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 0.508[0.020] 0.762[0.030] 0° ...
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... Document History Page Document Title: CY28RS400 Clock Generator for ATI Document Number: 38-07637 REV. ECN NO. Issue Date ** 204582 See ECN *A 215824 See ECN *B 278494 See ECN Document #: 38-07637 Rev. *B RS400 Chipset Orig. of Change RGL New data sheet RGL Minor Change: To post on the external web RGL Changed pins 10 and 11 from internal Pull up to Pull down ...