CY28437 SpectraLinear, CY28437 Datasheet - Page 9

• Manufacturer Part Number: CY28437
• Description: Clock Generator
• Manufacturer: SpectraLinear

Rev 1.0, November 20, 2006
Byte 10: Control Register 10 (continued)
Byte 11: Control Register 11
Byte 12: Control Register 12
Byte 13: Control Register 13
Bit
Bit
Bit
Bit
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
@Pup
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPU_DAF_M6
CPU_DAF_M5
CPU_DAF_M4
CPU_DAF_M3
CPU_DAF_M2
CPU_DAF_M1
CPU_DAF_M0
CPU_DAF_N7
CPU_DAF_N6
CPU_DAF_N5
CPU_DAF_N4
CPU_DAF_N3
CPU_DAF_N2
CPU_DAF_N1
CPU_DAF_N0
CPU_DAF_N8
SRC_N7
SRC_N6
SRC_N5
SRC_N4
SRC_N3
SRC_N2
SRC_N1
SRC_N0
WD_EN
Name
Name
Name
Name
Watchdog timer enable, when the bit is asserted, Watchdog timer is
triggered and time stamp of WD_Timer is loaded
0 = Disable, 1 = Enable
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[E:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used.
If Prog_CPU_EN is set, the values programmed is in CPU_FSEL_N[8:0]
and CPU_FSEL_M[6:0] will be used to determine the CPU output
frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[E:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used.
SRC Dial-A-Frequency Bit N7
SRC Dial-A-Frequency Bit N6
SRC Dial-A-Frequency Bit N5
SRC Dial-A-Frequency Bit N4
SRC Dial-A-Frequency Bit N3
SRC Dial-A-Frequency Bit N2
SRC Dial-A-Frequency Bit N1
SRC Dial-A-Frequency Bit N0
Description
Description
Description
Description
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CY28437
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