CY28437 SpectraLinear, CY28437 Datasheet - Page 5

• Manufacturer Part Number: CY28437
• Description: Clock Generator
• Manufacturer: SpectraLinear

Rev 1.0, November 20, 2006
Table 3. Byte Read and Byte Write Protocol (continued)
Control Registers
Byte 0: Control Register 0
Byte 1: Control Register 1
Bit
Bit
Bit
28
29
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
Acknowledge from slave
Stop
@Pup
@Pup
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
Byte Write Protocol
SRC[T/C]4_SATA
Description
RESERVED
DOT96[T/C]
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
CPU[T/C]1
CPU[T/C]0
USB_0
PCIF0
Name
Name
CPU
REF
SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4_SATA Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT96[T/C]MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_0 MHz Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
RESERVED, Set = 0
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
27:21
37:30
Bit
28
29
38
39
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Description
Description
Byte Read Protocol
Description
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CY28437
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