CY28158PVCT Cypress Semiconductor, CY28158PVCT Datasheet - Page 3

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CY28158PVCT

Manufacturer Part Number
CY28158PVCT
Description
Spread Spectrum Timing Solution for Serverworks Chipset
Manufacturer
Cypress Semiconductor
Datasheet
Function Table
Actual Clock Frequency Values
Clock Enable Configuration
Clock Driver Impedances
Document #: 38-07039 Rev. *B
0
0
0
0
1
1
1
1
CPU
CPU
48MHZ
CPU, IOAPIC
48MHZ, REF
PCI, 3V66
Note:
SEL133
CPU_STOP#
2.
3.
/100#
Buffer Name
TCLK is a test clock driven in on the X1 input in test mode.
This selection is defined as “N/A” or “Reserved.”
X
0
0
1
1
Clock Output
0
0
1
1
0
0
1
1
SEL1
PWR_DWN#
[2]
0
1
0
1
0
1
0
1
0
1
1
1
1
SEL0
2.375V – 2.625V
3.135V – 3.465V
3.135V – 3.465V
V
DD
Range
Hi-Z
100.227
100
100
TCLK/2
N/A
133.33
133.33
PCI_STOP#
(MHz)
CPU
X
0
1
0
1
Frequency
[3]
133.33
Target
(MHz)
100.0
48.0
Buffer Type
Hi-Z
66.818
66.67
66.67
TCLK/4
N/A
66.67
66.67
Type 1
Type 3
Type 5
LOW
LOW
LOW
CPU
(MHz)
ON
ON
3V66
[3]
3V66
LOW
LOW
LOW
Hi-Z
33.409
33.33
33.33
TCLK/8
N/A
33.33
33.33
ON
ON
(MHz)
Minimum
PCI
[3]
13.5
Frequency
20
12
132.769
LOW
LOW
LOW
Actual
99.126
48.008
PCI
(MHz)
ON
ON
Hi-Z
48.008
OFF
48.008
TCLK/2
N/A
OFF
48.008
48MHZ
(MHz)
PCI_F
LOW
ON
ON
ON
ON
[3]
[3]
[3]
Impedance
Typical
29
40
30
IOAPIC
Hi-Z
14.318
14.318
14.318
TCLK
N/A
14.318
14.318
LOW
REF
ON
ON
ON
ON
(MHz)
REF
[3]
–8740
–4208
PPM
OSC.
167
OFF
ON
ON
ON
ON
Maximum
Hi-Z
16.705
16.67
16.67
TCLK/16
N/A
16.67
16.67
CY28158
Page 3 of 10
IOAPIC
45
60
55
(MHz)
VCOs
[3]
OFF
ON
ON
ON
ON

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